Lines Matching refs:DSR
64 #define DSR 0x14 /* Status Reg */ macro
284 di_write_busy_wait(imxdi, DSR_CAF, DSR); in di_handle_valid_state()
334 di_write_busy_wait(imxdi, DSR_NVF, DSR); in di_handle_invalid_state()
336 di_write_busy_wait(imxdi, DSR_TCO, DSR); in di_handle_invalid_state()
343 return di_handle_valid_state(imxdi, __raw_readl(imxdi->ioaddr + DSR)); in di_handle_invalid_state()
386 DSR_MCO | DSR_TCO), DSR); in di_handle_invalid_and_failure_state()
388 dsr = readl(imxdi->ioaddr + DSR); in di_handle_invalid_and_failure_state()
400 di_write_busy_wait(imxdi, DSR_SVF, DSR); in di_handle_invalid_and_failure_state()
403 dsr = readl(imxdi->ioaddr + DSR); in di_handle_invalid_and_failure_state()
424 dsr = readl(imxdi->ioaddr + DSR); in di_handle_state()
488 writel(DSR_WEF, imxdi->ioaddr + DSR); in clear_write_error()
492 if ((readl(imxdi->ioaddr + DSR) & DSR_WEF) == 0) in clear_write_error()
571 dsr = readl(imxdi->ioaddr + DSR); in dryice_rtc_set_mmss()
630 alarm->pending = (readl(imxdi->ioaddr + DSR) & DSR_CAF) != 0; in dryice_rtc_read_alarm()
687 dsr = readl(imxdi->ioaddr + DSR); in dryice_irq()
753 di_write_wait(imxdi, DSR_CAF, DSR); in dryice_work()