115 	regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);  in stm32_pwm_raw_capture()
116 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);  in stm32_pwm_raw_capture()
122 	regmap_update_bits(priv->regmap, TIM_CCER, ccen, ccen);  in stm32_pwm_raw_capture()
160 	regmap_update_bits(priv->regmap, TIM_CCER, ccen, 0);  in stm32_pwm_raw_capture()
161 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);  in stm32_pwm_raw_capture()
208 	regmap_update_bits(priv->regmap,  in stm32_pwm_capture()
215 	regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ?  in stm32_pwm_capture()
262 	regmap_update_bits(priv->regmap,  in stm32_pwm_capture()
359 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);  in stm32_pwm_config()
373 		regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr);  in stm32_pwm_config()
375 		regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);  in stm32_pwm_config()
377 	regmap_update_bits(priv->regmap, TIM_BDTR,  in stm32_pwm_config()
393 	regmap_update_bits(priv->regmap, TIM_CCER, mask,  in stm32_pwm_set_polarity()
413 	regmap_update_bits(priv->regmap, TIM_CCER, mask, mask);  in stm32_pwm_enable()
416 	regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);  in stm32_pwm_enable()
419 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);  in stm32_pwm_enable()
433 	regmap_update_bits(priv->regmap, TIM_CCER, mask, 0);  in stm32_pwm_disable()
437 		regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);  in stm32_pwm_disable()
508 	regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr);  in stm32_pwm_set_breakinput()
558 	regmap_update_bits(priv->regmap,  in stm32_pwm_detect_complementary()
561 	regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE, 0);  in stm32_pwm_detect_complementary()
575 	regmap_update_bits(priv->regmap,  in stm32_pwm_detect_channels()
578 	regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE, 0);  in stm32_pwm_detect_channels()