109 	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);  in fsl_pwm_request()  local
111 	ret = clk_prepare_enable(fpc->ipg_clk);  in fsl_pwm_request()
112 	if (!ret && fpc->soc->has_enable_bits) {  in fsl_pwm_request()
113 		mutex_lock(&fpc->lock);  in fsl_pwm_request()
114 		regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16),  in fsl_pwm_request()
116 		mutex_unlock(&fpc->lock);  in fsl_pwm_request()
124 	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);  in fsl_pwm_free()  local
126 	if (fpc->soc->has_enable_bits) {  in fsl_pwm_free()
127 		mutex_lock(&fpc->lock);  in fsl_pwm_free()
128 		regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16),  in fsl_pwm_free()
130 		mutex_unlock(&fpc->lock);  in fsl_pwm_free()
133 	clk_disable_unprepare(fpc->ipg_clk);  in fsl_pwm_free()
136 static int fsl_pwm_calculate_default_ps(struct fsl_pwm_chip *fpc,  in fsl_pwm_calculate_default_ps()  argument
142 	sys_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_SYS]);  in fsl_pwm_calculate_default_ps()
146 	cnt_rate = clk_get_rate(fpc->clk[fpc->cnt_select]);  in fsl_pwm_calculate_default_ps()
152 		fpc->clk_ps = 1;  in fsl_pwm_calculate_default_ps()
157 		fpc->clk_ps = ratio;  in fsl_pwm_calculate_default_ps()
162 		fpc->clk_ps = ratio;  in fsl_pwm_calculate_default_ps()
171 static unsigned long fsl_pwm_calculate_cycles(struct fsl_pwm_chip *fpc,  in fsl_pwm_calculate_cycles()  argument
176 	c = clk_get_rate(fpc->clk[fpc->cnt_select]);  in fsl_pwm_calculate_cycles()
182 		do_div(c0, (1 << fpc->clk_ps));  in fsl_pwm_calculate_cycles()
185 	} while (++fpc->clk_ps < 8);  in fsl_pwm_calculate_cycles()
190 static unsigned long fsl_pwm_calculate_period_cycles(struct fsl_pwm_chip *fpc,  in fsl_pwm_calculate_period_cycles()  argument
196 	ret = fsl_pwm_calculate_default_ps(fpc, index);  in fsl_pwm_calculate_period_cycles()
198 		dev_err(fpc->chip.dev,  in fsl_pwm_calculate_period_cycles()
204 	return fsl_pwm_calculate_cycles(fpc, period_ns);  in fsl_pwm_calculate_period_cycles()
207 static unsigned long fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc,  in fsl_pwm_calculate_period()  argument
213 	cycles = fsl_pwm_calculate_period_cycles(fpc, period_ns,  in fsl_pwm_calculate_period()
216 		fpc->cnt_select = FSL_PWM_CLK_SYS;  in fsl_pwm_calculate_period()
220 	fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]);  in fsl_pwm_calculate_period()
221 	ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]);  in fsl_pwm_calculate_period()
231 	cycles = fsl_pwm_calculate_period_cycles(fpc, period_ns, m0);  in fsl_pwm_calculate_period()
233 		fpc->cnt_select = m0;  in fsl_pwm_calculate_period()
237 	fpc->cnt_select = m1;  in fsl_pwm_calculate_period()
239 	return fsl_pwm_calculate_period_cycles(fpc, period_ns, m1);  in fsl_pwm_calculate_period()
242 static unsigned long fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc,  in fsl_pwm_calculate_duty()  argument
249 	regmap_read(fpc->regmap, FTM_MOD, &val);  in fsl_pwm_calculate_duty()
259 	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);  in fsl_pwm_config()  local
262 	mutex_lock(&fpc->lock);  in fsl_pwm_config()
269 	if (fpc->period_ns && fpc->period_ns != period_ns) {  in fsl_pwm_config()
270 		dev_err(fpc->chip.dev,  in fsl_pwm_config()
273 		mutex_unlock(&fpc->lock);  in fsl_pwm_config()
277 	if (!fpc->period_ns && duty_ns) {  in fsl_pwm_config()
278 		period = fsl_pwm_calculate_period(fpc, period_ns);  in fsl_pwm_config()
280 			dev_err(fpc->chip.dev, "failed to calculate period\n");  in fsl_pwm_config()
281 			mutex_unlock(&fpc->lock);  in fsl_pwm_config()
285 		regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK,  in fsl_pwm_config()
286 				   fpc->clk_ps);  in fsl_pwm_config()
287 		regmap_write(fpc->regmap, FTM_MOD, period - 1);  in fsl_pwm_config()
289 		fpc->period_ns = period_ns;  in fsl_pwm_config()
292 	mutex_unlock(&fpc->lock);  in fsl_pwm_config()
294 	duty = fsl_pwm_calculate_duty(fpc, period_ns, duty_ns);  in fsl_pwm_config()
296 	regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm),  in fsl_pwm_config()
298 	regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty);  in fsl_pwm_config()
307 	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);  in fsl_pwm_set_polarity()  local
310 	regmap_read(fpc->regmap, FTM_POL, &val);  in fsl_pwm_set_polarity()
317 	regmap_write(fpc->regmap, FTM_POL, val);  in fsl_pwm_set_polarity()
322 static int fsl_counter_clock_enable(struct fsl_pwm_chip *fpc)  in fsl_counter_clock_enable()  argument
327 	regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK,  in fsl_counter_clock_enable()
328 			   FTM_SC_CLK(fpc->cnt_select));  in fsl_counter_clock_enable()
330 	ret = clk_prepare_enable(fpc->clk[fpc->cnt_select]);  in fsl_counter_clock_enable()
334 	ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);  in fsl_counter_clock_enable()
336 		clk_disable_unprepare(fpc->clk[fpc->cnt_select]);  in fsl_counter_clock_enable()
345 	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);  in fsl_pwm_enable()  local
348 	mutex_lock(&fpc->lock);  in fsl_pwm_enable()
349 	regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm), 0);  in fsl_pwm_enable()
351 	ret = fsl_counter_clock_enable(fpc);  in fsl_pwm_enable()
352 	mutex_unlock(&fpc->lock);  in fsl_pwm_enable()
359 	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);  in fsl_pwm_disable()  local
362 	mutex_lock(&fpc->lock);  in fsl_pwm_disable()
363 	regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm),  in fsl_pwm_disable()
366 	clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);  in fsl_pwm_disable()
367 	clk_disable_unprepare(fpc->clk[fpc->cnt_select]);  in fsl_pwm_disable()
369 	regmap_read(fpc->regmap, FTM_OUTMASK, &val);  in fsl_pwm_disable()
371 		fpc->period_ns = 0;  in fsl_pwm_disable()
373 	mutex_unlock(&fpc->lock);  in fsl_pwm_disable()
386 static int fsl_pwm_init(struct fsl_pwm_chip *fpc)  in fsl_pwm_init()  argument
390 	ret = clk_prepare_enable(fpc->ipg_clk);  in fsl_pwm_init()
394 	regmap_write(fpc->regmap, FTM_CNTIN, 0x00);  in fsl_pwm_init()
395 	regmap_write(fpc->regmap, FTM_OUTINIT, 0x00);  in fsl_pwm_init()
396 	regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF);  in fsl_pwm_init()
398 	clk_disable_unprepare(fpc->ipg_clk);  in fsl_pwm_init()
424 	struct fsl_pwm_chip *fpc;  in fsl_pwm_probe()  local
429 	fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL);  in fsl_pwm_probe()
430 	if (!fpc)  in fsl_pwm_probe()
433 	mutex_init(&fpc->lock);  in fsl_pwm_probe()
435 	fpc->soc = of_device_get_match_data(&pdev->dev);  in fsl_pwm_probe()
436 	fpc->chip.dev = &pdev->dev;  in fsl_pwm_probe()
443 	fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base,  in fsl_pwm_probe()
445 	if (IS_ERR(fpc->regmap)) {  in fsl_pwm_probe()
447 		return PTR_ERR(fpc->regmap);  in fsl_pwm_probe()
450 	fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys");  in fsl_pwm_probe()
451 	if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) {  in fsl_pwm_probe()
453 		return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]);  in fsl_pwm_probe()
456 	fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix");  in fsl_pwm_probe()
457 	if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX]))  in fsl_pwm_probe()
458 		return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]);  in fsl_pwm_probe()
460 	fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext");  in fsl_pwm_probe()
461 	if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT]))  in fsl_pwm_probe()
462 		return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]);  in fsl_pwm_probe()
464 	fpc->clk[FSL_PWM_CLK_CNTEN] =  in fsl_pwm_probe()
465 				devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en");  in fsl_pwm_probe()
466 	if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]))  in fsl_pwm_probe()
467 		return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]);  in fsl_pwm_probe()
473 	fpc->ipg_clk = devm_clk_get(&pdev->dev, "ipg");  in fsl_pwm_probe()
474 	if (IS_ERR(fpc->ipg_clk))  in fsl_pwm_probe()
475 		fpc->ipg_clk = fpc->clk[FSL_PWM_CLK_SYS];  in fsl_pwm_probe()
478 	fpc->chip.ops = &fsl_pwm_ops;  in fsl_pwm_probe()
479 	fpc->chip.of_xlate = of_pwm_xlate_with_flags;  in fsl_pwm_probe()
480 	fpc->chip.of_pwm_n_cells = 3;  in fsl_pwm_probe()
481 	fpc->chip.base = -1;  in fsl_pwm_probe()
482 	fpc->chip.npwm = 8;  in fsl_pwm_probe()
484 	ret = pwmchip_add(&fpc->chip);  in fsl_pwm_probe()
490 	platform_set_drvdata(pdev, fpc);  in fsl_pwm_probe()
492 	return fsl_pwm_init(fpc);  in fsl_pwm_probe()
497 	struct fsl_pwm_chip *fpc = platform_get_drvdata(pdev);  in fsl_pwm_remove()  local
499 	return pwmchip_remove(&fpc->chip);  in fsl_pwm_remove()
505 	struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);  in fsl_pwm_suspend()  local
508 	regcache_cache_only(fpc->regmap, true);  in fsl_pwm_suspend()
509 	regcache_mark_dirty(fpc->regmap);  in fsl_pwm_suspend()
511 	for (i = 0; i < fpc->chip.npwm; i++) {  in fsl_pwm_suspend()
512 		struct pwm_device *pwm = &fpc->chip.pwms[i];  in fsl_pwm_suspend()
517 		clk_disable_unprepare(fpc->ipg_clk);  in fsl_pwm_suspend()
522 		clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);  in fsl_pwm_suspend()
523 		clk_disable_unprepare(fpc->clk[fpc->cnt_select]);  in fsl_pwm_suspend()
531 	struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);  in fsl_pwm_resume()  local
534 	for (i = 0; i < fpc->chip.npwm; i++) {  in fsl_pwm_resume()
535 		struct pwm_device *pwm = &fpc->chip.pwms[i];  in fsl_pwm_resume()
540 		clk_prepare_enable(fpc->ipg_clk);  in fsl_pwm_resume()
545 		clk_prepare_enable(fpc->clk[fpc->cnt_select]);  in fsl_pwm_resume()
546 		clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);  in fsl_pwm_resume()
550 	regcache_cache_only(fpc->regmap, false);  in fsl_pwm_resume()
551 	regcache_sync(fpc->regmap);  in fsl_pwm_resume()