Lines Matching refs:pctl_readl
835 static inline u32 pctl_readl(struct pistachio_pinctrl *pctl, u32 reg) in pctl_readl() function
968 val = pctl_readl(pctl, pg->mux_reg); in pistachio_pinmux_enable()
981 val = pctl_readl(pctl, pf->scenario_reg); in pistachio_pinmux_enable()
1011 val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin)); in pistachio_pinconf_get()
1015 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >> in pistachio_pinconf_get()
1020 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >> in pistachio_pinconf_get()
1025 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >> in pistachio_pinconf_get()
1030 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >> in pistachio_pinconf_get()
1035 val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin)); in pistachio_pinconf_get()
1039 val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin)) >> in pistachio_pinconf_get()
1081 val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin)); in pistachio_pinconf_set()
1089 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)); in pistachio_pinconf_set()
1095 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)); in pistachio_pinconf_set()
1101 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)); in pistachio_pinconf_set()
1107 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)); in pistachio_pinconf_set()
1113 val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin)); in pistachio_pinconf_set()
1121 val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin)); in pistachio_pinconf_set()