Lines Matching refs:PIC32_SET
1827 writel(mask, bank->reg_base + PIC32_SET(TRIS_REG)); in pic32_gpio_direction_input()
1846 writel(mask, bank->reg_base + PIC32_SET(PORT_REG)); in pic32_gpio_set()
1948 writel(mask, bank->reg_base +PIC32_SET(CNPU_REG)); in pic32_pinconf_set()
1952 writel(mask, bank->reg_base + PIC32_SET(CNPD_REG)); in pic32_pinconf_set()
1960 writel(mask, bank->reg_base + PIC32_SET(ANSEL_REG)); in pic32_pinconf_set()
1964 writel(mask, bank->reg_base + PIC32_SET(ODCU_REG)); in pic32_pinconf_set()
2022 writel(BIT(PIC32_CNCON_ON), bank->reg_base + PIC32_SET(CNCON_REG)); in pic32_gpio_irq_unmask()
2043 writel(mask, bank->reg_base + PIC32_SET(CNEN_REG)); in pic32_gpio_irq_set_type()
2047 writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG)); in pic32_gpio_irq_set_type()
2053 writel(mask, bank->reg_base + PIC32_SET(CNNE_REG)); in pic32_gpio_irq_set_type()
2055 writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG)); in pic32_gpio_irq_set_type()
2059 writel(mask, bank->reg_base + PIC32_SET(CNEN_REG)); in pic32_gpio_irq_set_type()
2061 writel(mask, bank->reg_base + PIC32_SET(CNNE_REG)); in pic32_gpio_irq_set_type()
2063 writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG)); in pic32_gpio_irq_set_type()