Lines Matching refs:pin_reg
46 u32 pin_reg; in amd_gpio_get_direction() local
50 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_get_direction()
53 return !(pin_reg & BIT(OUTPUT_ENABLE_OFF)); in amd_gpio_get_direction()
59 u32 pin_reg; in amd_gpio_direction_input() local
63 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_direction_input()
64 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); in amd_gpio_direction_input()
65 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_direction_input()
74 u32 pin_reg; in amd_gpio_direction_output() local
79 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_direction_output()
80 pin_reg |= BIT(OUTPUT_ENABLE_OFF); in amd_gpio_direction_output()
82 pin_reg |= BIT(OUTPUT_VALUE_OFF); in amd_gpio_direction_output()
84 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); in amd_gpio_direction_output()
85 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_direction_output()
93 u32 pin_reg; in amd_gpio_get_value() local
98 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_get_value()
101 return !!(pin_reg & BIT(PIN_STS_OFF)); in amd_gpio_get_value()
106 u32 pin_reg; in amd_gpio_set_value() local
111 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_set_value()
113 pin_reg |= BIT(OUTPUT_VALUE_OFF); in amd_gpio_set_value()
115 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); in amd_gpio_set_value()
116 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_set_value()
124 u32 pin_reg; in amd_gpio_set_debounce() local
130 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_set_debounce()
133 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; in amd_gpio_set_debounce()
134 pin_reg &= ~DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
146 pin_reg |= 1; in amd_gpio_set_debounce()
147 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
148 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
151 pin_reg |= time & DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
152 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
153 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
156 pin_reg |= time & DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
157 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
158 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
161 pin_reg |= time & DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
162 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
163 pin_reg |= BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
166 pin_reg |= time & DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
167 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
168 pin_reg |= BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
170 pin_reg &= ~DB_CNTRl_MASK; in amd_gpio_set_debounce()
174 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
175 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
176 pin_reg &= ~DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
177 pin_reg &= ~DB_CNTRl_MASK; in amd_gpio_set_debounce()
179 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_set_debounce()
200 u32 pin_reg; in amd_gpio_dbg_show() local
246 pin_reg = readl(gpio_dev->base + i * 4); in amd_gpio_dbg_show()
249 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { in amd_gpio_dbg_show()
250 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) & in amd_gpio_dbg_show()
258 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) && in amd_gpio_dbg_show()
264 if (pin_reg & BIT(LEVEL_TRIG_OFF)) in amd_gpio_dbg_show()
276 if (pin_reg & BIT(INTERRUPT_MASK_OFF)) in amd_gpio_dbg_show()
283 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) in amd_gpio_dbg_show()
288 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) in amd_gpio_dbg_show()
293 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) in amd_gpio_dbg_show()
298 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { in amd_gpio_dbg_show()
300 if (pin_reg & BIT(PULL_UP_SEL_OFF)) in amd_gpio_dbg_show()
309 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) in amd_gpio_dbg_show()
314 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { in amd_gpio_dbg_show()
317 if (pin_reg & BIT(OUTPUT_VALUE_OFF)) in amd_gpio_dbg_show()
325 if (pin_reg & BIT(PIN_STS_OFF)) in amd_gpio_dbg_show()
337 output_value, output_enable, pin_reg); in amd_gpio_dbg_show()
347 u32 pin_reg; in amd_gpio_irq_enable() local
353 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_enable()
354 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); in amd_gpio_irq_enable()
355 pin_reg |= BIT(INTERRUPT_MASK_OFF); in amd_gpio_irq_enable()
356 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_enable()
362 u32 pin_reg; in amd_gpio_irq_disable() local
368 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_disable()
369 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); in amd_gpio_irq_disable()
370 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); in amd_gpio_irq_disable()
371 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_disable()
377 u32 pin_reg; in amd_gpio_irq_mask() local
383 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_mask()
384 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); in amd_gpio_irq_mask()
385 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_mask()
391 u32 pin_reg; in amd_gpio_irq_unmask() local
397 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_unmask()
398 pin_reg |= BIT(INTERRUPT_MASK_OFF); in amd_gpio_irq_unmask()
399 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_unmask()
420 u32 pin_reg, pin_reg_irq_en, mask; in amd_gpio_irq_set_type() local
426 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_set_type()
439 pin_reg &= ~BIT(LEVEL_TRIG_OFF); in amd_gpio_irq_set_type()
440 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); in amd_gpio_irq_set_type()
441 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; in amd_gpio_irq_set_type()
442 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; in amd_gpio_irq_set_type()
447 pin_reg &= ~BIT(LEVEL_TRIG_OFF); in amd_gpio_irq_set_type()
448 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); in amd_gpio_irq_set_type()
449 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; in amd_gpio_irq_set_type()
450 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; in amd_gpio_irq_set_type()
455 pin_reg &= ~BIT(LEVEL_TRIG_OFF); in amd_gpio_irq_set_type()
456 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); in amd_gpio_irq_set_type()
457 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; in amd_gpio_irq_set_type()
458 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; in amd_gpio_irq_set_type()
463 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; in amd_gpio_irq_set_type()
464 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); in amd_gpio_irq_set_type()
465 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; in amd_gpio_irq_set_type()
466 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); in amd_gpio_irq_set_type()
467 pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF; in amd_gpio_irq_set_type()
472 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; in amd_gpio_irq_set_type()
473 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); in amd_gpio_irq_set_type()
474 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; in amd_gpio_irq_set_type()
475 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); in amd_gpio_irq_set_type()
476 pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF; in amd_gpio_irq_set_type()
488 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; in amd_gpio_irq_set_type()
505 pin_reg_irq_en = pin_reg; in amd_gpio_irq_set_type()
511 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_set_type()
638 u32 pin_reg; in amd_pinconf_get() local
645 pin_reg = readl(gpio_dev->base + pin*4); in amd_pinconf_get()
649 arg = pin_reg & DB_TMR_OUT_MASK; in amd_pinconf_get()
653 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); in amd_pinconf_get()
657 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); in amd_pinconf_get()
661 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; in amd_pinconf_get()
681 u32 pin_reg; in amd_pinconf_set() local
690 pin_reg = readl(gpio_dev->base + pin*4); in amd_pinconf_set()
694 pin_reg &= ~DB_TMR_OUT_MASK; in amd_pinconf_set()
695 pin_reg |= arg & DB_TMR_OUT_MASK; in amd_pinconf_set()
699 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); in amd_pinconf_set()
700 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; in amd_pinconf_set()
704 pin_reg &= ~BIT(PULL_UP_SEL_OFF); in amd_pinconf_set()
705 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; in amd_pinconf_set()
706 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); in amd_pinconf_set()
707 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; in amd_pinconf_set()
711 pin_reg &= ~(DRV_STRENGTH_SEL_MASK in amd_pinconf_set()
713 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) in amd_pinconf_set()
723 writel(pin_reg, gpio_dev->base + pin*4); in amd_pinconf_set()