50 static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint,  in mtk_eint_get_offset()  argument
57 	if (eint_num >= eint->hw->ap_num)  in mtk_eint_get_offset()
58 		eint_base = eint->hw->ap_num;  in mtk_eint_get_offset()
60 	reg = eint->base + offset + ((eint_num - eint_base) / 32) * 4;  in mtk_eint_get_offset()
65 static unsigned int mtk_eint_can_en_debounce(struct mtk_eint *eint,  in mtk_eint_can_en_debounce()  argument
70 	void __iomem *reg = mtk_eint_get_offset(eint, eint_num,  in mtk_eint_can_en_debounce()
71 						eint->regs->sens);  in mtk_eint_can_en_debounce()
78 	if (eint_num < eint->hw->db_cnt && sens != MTK_EINT_EDGE_SENSITIVE)  in mtk_eint_can_en_debounce()
84 static int mtk_eint_flip_edge(struct mtk_eint *eint, int hwirq)  in mtk_eint_flip_edge()  argument
89 	u32 port = (hwirq >> 5) & eint->hw->port_mask;  in mtk_eint_flip_edge()
90 	void __iomem *reg = eint->base + (port << 2);  in mtk_eint_flip_edge()
92 	curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl, hwirq);  in mtk_eint_flip_edge()
97 			reg_offset = eint->regs->pol_clr;  in mtk_eint_flip_edge()
99 			reg_offset = eint->regs->pol_set;  in mtk_eint_flip_edge()
102 		curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl,  in mtk_eint_flip_edge()
111 	struct mtk_eint *eint = irq_data_get_irq_chip_data(d);  in mtk_eint_mask()  local
113 	void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,  in mtk_eint_mask()
114 						eint->regs->mask_set);  in mtk_eint_mask()
121 	struct mtk_eint *eint = irq_data_get_irq_chip_data(d);  in mtk_eint_unmask()  local
123 	void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,  in mtk_eint_unmask()
124 						eint->regs->mask_clr);  in mtk_eint_unmask()
128 	if (eint->dual_edge[d->hwirq])  in mtk_eint_unmask()
129 		mtk_eint_flip_edge(eint, d->hwirq);  in mtk_eint_unmask()
132 static unsigned int mtk_eint_get_mask(struct mtk_eint *eint,  in mtk_eint_get_mask()  argument
136 	void __iomem *reg = mtk_eint_get_offset(eint, eint_num,  in mtk_eint_get_mask()
137 						eint->regs->mask);  in mtk_eint_get_mask()
144 	struct mtk_eint *eint = irq_data_get_irq_chip_data(d);  in mtk_eint_ack()  local
146 	void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,  in mtk_eint_ack()
147 						eint->regs->ack);  in mtk_eint_ack()
154 	struct mtk_eint *eint = irq_data_get_irq_chip_data(d);  in mtk_eint_set_type()  local
160 		dev_err(eint->dev,  in mtk_eint_set_type()
167 		eint->dual_edge[d->hwirq] = 1;  in mtk_eint_set_type()
169 		eint->dual_edge[d->hwirq] = 0;  in mtk_eint_set_type()
172 		reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_clr);  in mtk_eint_set_type()
175 		reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_set);  in mtk_eint_set_type()
180 		reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_clr);  in mtk_eint_set_type()
183 		reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_set);  in mtk_eint_set_type()
187 	if (eint->dual_edge[d->hwirq])  in mtk_eint_set_type()
188 		mtk_eint_flip_edge(eint, d->hwirq);  in mtk_eint_set_type()
195 	struct mtk_eint *eint = irq_data_get_irq_chip_data(d);  in mtk_eint_irq_set_wake()  local
200 		eint->wake_mask[reg] |= BIT(shift);  in mtk_eint_irq_set_wake()
202 		eint->wake_mask[reg] &= ~BIT(shift);  in mtk_eint_irq_set_wake()
207 static void mtk_eint_chip_write_mask(const struct mtk_eint *eint,  in mtk_eint_chip_write_mask()  argument
213 	for (port = 0; port < eint->hw->ports; port++) {  in mtk_eint_chip_write_mask()
215 		writel_relaxed(~buf[port], reg + eint->regs->mask_set);  in mtk_eint_chip_write_mask()
216 		writel_relaxed(buf[port], reg + eint->regs->mask_clr);  in mtk_eint_chip_write_mask()
220 static void mtk_eint_chip_read_mask(const struct mtk_eint *eint,  in mtk_eint_chip_read_mask()  argument
226 	for (port = 0; port < eint->hw->ports; port++) {  in mtk_eint_chip_read_mask()
227 		reg = base + eint->regs->mask + (port << 2);  in mtk_eint_chip_read_mask()
235 	struct mtk_eint *eint = irq_data_get_irq_chip_data(d);  in mtk_eint_irq_request_resources()  local
240 	err = eint->gpio_xlate->get_gpio_n(eint->pctl, d->hwirq,  in mtk_eint_irq_request_resources()
243 		dev_err(eint->dev, "Can not find pin\n");  in mtk_eint_irq_request_resources()
249 		dev_err(eint->dev, "unable to lock HW IRQ %lu for IRQ\n",  in mtk_eint_irq_request_resources()
254 	err = eint->gpio_xlate->set_gpio_as_eint(eint->pctl, d->hwirq);  in mtk_eint_irq_request_resources()
256 		dev_err(eint->dev, "Can not eint mode\n");  in mtk_eint_irq_request_resources()
265 	struct mtk_eint *eint = irq_data_get_irq_chip_data(d);  in mtk_eint_irq_release_resources()  local
269 	eint->gpio_xlate->get_gpio_n(eint->pctl, d->hwirq, &gpio_n,  in mtk_eint_irq_release_resources()
287 static unsigned int mtk_eint_hw_init(struct mtk_eint *eint)  in mtk_eint_hw_init()  argument
289 	void __iomem *reg = eint->base + eint->regs->dom_en;  in mtk_eint_hw_init()
292 	for (i = 0; i < eint->hw->ap_num; i += 32) {  in mtk_eint_hw_init()
301 mtk_eint_debounce_process(struct mtk_eint *eint, int index)  in mtk_eint_debounce_process()  argument
306 	ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_ctrl;  in mtk_eint_debounce_process()
307 	dbnc = readl(eint->base + ctrl_offset);  in mtk_eint_debounce_process()
310 		ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_set;  in mtk_eint_debounce_process()
312 		writel(rst, eint->base + ctrl_offset);  in mtk_eint_debounce_process()
319 	struct mtk_eint *eint = irq_desc_get_handler_data(desc);  in mtk_eint_irq_handler()  local
322 	void __iomem *reg =  mtk_eint_get_offset(eint, 0, eint->regs->stat);  in mtk_eint_irq_handler()
326 	for (eint_num = 0; eint_num < eint->hw->ap_num; eint_num += 32,  in mtk_eint_irq_handler()
332 			virq = irq_find_mapping(eint->domain, index);  in mtk_eint_irq_handler()
335 			dual_edge = eint->dual_edge[index];  in mtk_eint_irq_handler()
341 				writel(BIT(offset), reg - eint->regs->stat +  in mtk_eint_irq_handler()
342 				       eint->regs->soft_clr);  in mtk_eint_irq_handler()
345 				eint->gpio_xlate->get_gpio_state(eint->pctl,  in mtk_eint_irq_handler()
352 				curr_level = mtk_eint_flip_edge(eint, index);  in mtk_eint_irq_handler()
360 					       eint->regs->stat +  in mtk_eint_irq_handler()
361 					       eint->regs->soft_set);  in mtk_eint_irq_handler()
364 			if (index < eint->hw->db_cnt)  in mtk_eint_irq_handler()
365 				mtk_eint_debounce_process(eint, index);  in mtk_eint_irq_handler()
371 int mtk_eint_do_suspend(struct mtk_eint *eint)  in mtk_eint_do_suspend()  argument
373 	mtk_eint_chip_read_mask(eint, eint->base, eint->cur_mask);  in mtk_eint_do_suspend()
374 	mtk_eint_chip_write_mask(eint, eint->base, eint->wake_mask);  in mtk_eint_do_suspend()
379 int mtk_eint_do_resume(struct mtk_eint *eint)  in mtk_eint_do_resume()  argument
381 	mtk_eint_chip_write_mask(eint, eint->base, eint->cur_mask);  in mtk_eint_do_resume()
386 int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_num,  in mtk_eint_set_debounce()  argument
396 	virq = irq_find_mapping(eint->domain, eint_num);  in mtk_eint_set_debounce()
400 	set_offset = (eint_num / 4) * 4 + eint->regs->dbnc_set;  in mtk_eint_set_debounce()
401 	clr_offset = (eint_num / 4) * 4 + eint->regs->dbnc_clr;  in mtk_eint_set_debounce()
403 	if (!mtk_eint_can_en_debounce(eint, eint_num))  in mtk_eint_set_debounce()
414 	if (!mtk_eint_get_mask(eint, eint_num)) {  in mtk_eint_set_debounce()
422 	writel(clr_bit, eint->base + clr_offset);  in mtk_eint_set_debounce()
427 	writel(rst | bit, eint->base + set_offset);  in mtk_eint_set_debounce()
440 int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n)  in mtk_eint_find_irq()  argument
444 	irq = irq_find_mapping(eint->domain, eint_n);  in mtk_eint_find_irq()
451 int mtk_eint_do_init(struct mtk_eint *eint)  in mtk_eint_do_init()  argument
456 	if (!eint->regs)  in mtk_eint_do_init()
457 		eint->regs = &mtk_generic_eint_regs;  in mtk_eint_do_init()
459 	eint->wake_mask = devm_kcalloc(eint->dev, eint->hw->ports,  in mtk_eint_do_init()
460 				       sizeof(*eint->wake_mask), GFP_KERNEL);  in mtk_eint_do_init()
461 	if (!eint->wake_mask)  in mtk_eint_do_init()
464 	eint->cur_mask = devm_kcalloc(eint->dev, eint->hw->ports,  in mtk_eint_do_init()
465 				      sizeof(*eint->cur_mask), GFP_KERNEL);  in mtk_eint_do_init()
466 	if (!eint->cur_mask)  in mtk_eint_do_init()
469 	eint->dual_edge = devm_kcalloc(eint->dev, eint->hw->ap_num,  in mtk_eint_do_init()
471 	if (!eint->dual_edge)  in mtk_eint_do_init()
474 	eint->domain = irq_domain_add_linear(eint->dev->of_node,  in mtk_eint_do_init()
475 					     eint->hw->ap_num,  in mtk_eint_do_init()
477 	if (!eint->domain)  in mtk_eint_do_init()
480 	mtk_eint_hw_init(eint);  in mtk_eint_do_init()
481 	for (i = 0; i < eint->hw->ap_num; i++) {  in mtk_eint_do_init()
482 		int virq = irq_create_mapping(eint->domain, i);  in mtk_eint_do_init()
486 		irq_set_chip_data(virq, eint);  in mtk_eint_do_init()
489 	irq_set_chained_handler_and_data(eint->irq, mtk_eint_irq_handler,  in mtk_eint_do_init()
490 					 eint);  in mtk_eint_do_init()