Lines Matching refs:ASPEED_IP_SCU
440 #define BOOT_SRC_NOR { ASPEED_IP_SCU, HW_STRAP1, GENMASK(1, 0), 0, 0 }
501 { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 }
503 { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 2, 0 }
505 { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 }
653 #define VPI18_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 }
654 #define VPI24_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 2, 0 }
655 #define VPI30_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 3, 0 }
1039 #define VPOOFF0_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
1040 #define VPO12_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 1, 0 }
1041 #define VPO24_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 2, 0 }
1042 #define VPOOFF1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 3, 0 }
1043 #define VPO_OFF_12 { ASPEED_IP_SCU, SCU94, 0x2, 0, 0 }