231 	const struct rockchip_usb2phy_cfg	*phy_cfg;  member
275 	if (!property_enabled(base, &rphy->phy_cfg->clkout_ctl)) {  in rockchip_usb2phy_clk480m_prepare()
276 		ret = property_enable(base, &rphy->phy_cfg->clkout_ctl, true);  in rockchip_usb2phy_clk480m_prepare()
294 	property_enable(base, &rphy->phy_cfg->clkout_ctl, false);  in rockchip_usb2phy_clk480m_unprepare()
303 	return property_enabled(base, &rphy->phy_cfg->clkout_ctl);  in rockchip_usb2phy_clk480m_prepared()
672 	property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);  in rockchip_chg_enable_dcd()
673 	property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en);  in rockchip_chg_enable_dcd()
681 	property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en);  in rockchip_chg_enable_primary_det()
682 	property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en);  in rockchip_chg_enable_primary_det()
690 	property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en);  in rockchip_chg_enable_secondary_det()
691 	property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en);  in rockchip_chg_enable_secondary_det()
714 		property_enable(base, &rphy->phy_cfg->chg_det.opmode, false);  in rockchip_chg_detect_work()
724 					  &rphy->phy_cfg->chg_det.dp_det);  in rockchip_chg_detect_work()
742 					&rphy->phy_cfg->chg_det.cp_det);  in rockchip_chg_detect_work()
764 					&rphy->phy_cfg->chg_det.dcp_det);  in rockchip_chg_detect_work()
778 		property_enable(base, &rphy->phy_cfg->chg_det.opmode, true);  in rockchip_chg_detect_work()
958 	rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];  in rockchip_usb2phy_host_port_init()
1000 	rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];  in rockchip_usb2phy_otg_port_init()
1138 			rphy->phy_cfg = &phy_cfgs[index];  in rockchip_usb2phy_probe()
1145 	if (!rphy->phy_cfg) {  in rockchip_usb2phy_probe()
1200 		if (++index >= rphy->phy_cfg->num_ports)  in rockchip_usb2phy_probe()