104 	struct hw_pmu_info *inf;  member
151 	struct hw_pmu_info inf;  member
746 	return readl(pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));  in xgene_pmu_read_counter32()
771 	writel(val, pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));  in xgene_pmu_write_counter32()
790 	writel(val, pmu_dev->inf->csr + PMU_PMEVTYPER0 + (4 * idx));  in xgene_pmu_write_evttype()
796 	writel(val, pmu_dev->inf->csr + PMU_PMAMR0);  in xgene_pmu_write_agentmsk()
805 	writel(val, pmu_dev->inf->csr + PMU_PMAMR1);  in xgene_pmu_write_agent1msk()
816 	val = readl(pmu_dev->inf->csr + PMU_PMCNTENSET);  in xgene_pmu_enable_counter()
818 	writel(val, pmu_dev->inf->csr + PMU_PMCNTENSET);  in xgene_pmu_enable_counter()
826 	val = readl(pmu_dev->inf->csr + PMU_PMCNTENCLR);  in xgene_pmu_disable_counter()
828 	writel(val, pmu_dev->inf->csr + PMU_PMCNTENCLR);  in xgene_pmu_disable_counter()
836 	val = readl(pmu_dev->inf->csr + PMU_PMINTENSET);  in xgene_pmu_enable_counter_int()
838 	writel(val, pmu_dev->inf->csr + PMU_PMINTENSET);  in xgene_pmu_enable_counter_int()
846 	val = readl(pmu_dev->inf->csr + PMU_PMINTENCLR);  in xgene_pmu_disable_counter_int()
848 	writel(val, pmu_dev->inf->csr + PMU_PMINTENCLR);  in xgene_pmu_disable_counter_int()
855 	val = readl(pmu_dev->inf->csr + PMU_PMCR);  in xgene_pmu_reset_counters()
857 	writel(val, pmu_dev->inf->csr + PMU_PMCR);  in xgene_pmu_reset_counters()
864 	val = readl(pmu_dev->inf->csr + PMU_PMCR);  in xgene_pmu_start_counters()
866 	writel(val, pmu_dev->inf->csr + PMU_PMCR);  in xgene_pmu_start_counters()
873 	val = readl(pmu_dev->inf->csr + PMU_PMCR);  in xgene_pmu_stop_counters()
875 	writel(val, pmu_dev->inf->csr + PMU_PMCR);  in xgene_pmu_stop_counters()
969 	if (pmu_dev->inf->type == PMU_TYPE_IOB)  in xgene_perf_enable_event()
1155 	pmu->inf = &ctx->inf;  in xgene_pmu_dev_add()
1158 	switch (pmu->inf->type) {  in xgene_pmu_dev_add()
1160 		if (!(xgene_pmu->l3c_active_mask & pmu->inf->enable_mask))  in xgene_pmu_dev_add()
1178 		if (!(xgene_pmu->mcb_active_mask & pmu->inf->enable_mask))  in xgene_pmu_dev_add()
1186 		if (!(xgene_pmu->mc_active_mask & pmu->inf->enable_mask))  in xgene_pmu_dev_add()
1210 	void __iomem *csr = pmu_dev->inf->csr;  in _xgene_pmu_isr()
1496 	struct hw_pmu_info *inf;  in acpi_get_pmu_hw_inf()  local
1534 	inf = &ctx->inf;  in acpi_get_pmu_hw_inf()
1535 	inf->type = type;  in acpi_get_pmu_hw_inf()
1536 	inf->csr = dev_csr;  in acpi_get_pmu_hw_inf()
1537 	inf->enable_mask = 1 << enable_bit;  in acpi_get_pmu_hw_inf()
1599 	switch (ctx->inf.type) {  in acpi_pmu_dev_add()
1653 	struct hw_pmu_info *inf;  in fdt_get_pmu_hw_inf()  local
1683 	inf = &ctx->inf;  in fdt_get_pmu_hw_inf()
1684 	inf->type = type;  in fdt_get_pmu_hw_inf()
1685 	inf->csr = dev_csr;  in fdt_get_pmu_hw_inf()
1686 	inf->enable_mask = 1 << enable_bit;  in fdt_get_pmu_hw_inf()
1721 		switch (ctx->inf.type) {  in fdt_pmu_probe_pmu_dev()