Lines Matching refs:dwreg
482 struct aspm_register_info *dwreg) in aspm_calc_l1ss_info() argument
488 link->l1ss.dw_cap_ptr = dwreg->l1ss_cap_ptr; in aspm_calc_l1ss_info()
496 val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8; in aspm_calc_l1ss_info()
502 val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19; in aspm_calc_l1ss_info()
503 scale2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16; in aspm_calc_l1ss_info()
533 struct aspm_register_info upreg, dwreg; in pcie_aspm_cap_init() local
544 pcie_get_aspm_reg(child, &dwreg); in pcie_aspm_cap_init()
550 if (!(upreg.support & dwreg.support)) in pcie_aspm_cap_init()
561 pcie_get_aspm_reg(child, &dwreg); in pcie_aspm_cap_init()
570 if (dwreg.support & upreg.support & PCIE_LINK_STATE_L0S) in pcie_aspm_cap_init()
572 if (dwreg.enabled & PCIE_LINK_STATE_L0S) in pcie_aspm_cap_init()
577 link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s); in pcie_aspm_cap_init()
580 if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1) in pcie_aspm_cap_init()
582 if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1) in pcie_aspm_cap_init()
585 link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1); in pcie_aspm_cap_init()
588 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1) in pcie_aspm_cap_init()
590 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2) in pcie_aspm_cap_init()
592 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1) in pcie_aspm_cap_init()
594 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2) in pcie_aspm_cap_init()
597 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1) in pcie_aspm_cap_init()
599 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2) in pcie_aspm_cap_init()
601 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1) in pcie_aspm_cap_init()
603 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2) in pcie_aspm_cap_init()
607 aspm_calc_l1ss_info(link, &upreg, &dwreg); in pcie_aspm_cap_init()