Lines Matching defs:pcie_link_state
50 struct pcie_link_state { struct
53 struct pcie_link_state *root; /* pointer to the root port link */ argument
54 struct pcie_link_state *parent; /* pointer to the parent Link state */ argument
55 struct list_head sibling; /* node in link_list */
56 struct list_head children; /* list of child link states */
57 struct list_head link; /* node in parent's children list */
60 u32 aspm_support:7; /* Supported ASPM state */
61 u32 aspm_enabled:7; /* Enabled ASPM state */
62 u32 aspm_capable:7; /* Capable ASPM state with latency */
63 u32 aspm_default:7; /* Default ASPM state by BIOS */
64 u32 aspm_disable:7; /* Disabled ASPM state */
67 u32 clkpm_capable:1; /* Clock PM capable? */
68 u32 clkpm_enabled:1; /* Current Clock PM state */
69 u32 clkpm_default:1; /* Default Clock PM state by BIOS */
72 struct aspm_latency latency_up; /* Upstream direction exit latency */
73 struct aspm_latency latency_dw; /* Downstream direction exit latency */
78 struct aspm_latency acceptable[8];
81 struct {
86 } l1ss;