126 	u32 revision = fields[1].integer.value;  in decode_type0_hpx_record()
137 		hpx->t0->cache_line_size = fields[2].integer.value;  in decode_type0_hpx_record()
138 		hpx->t0->latency_timer   = fields[3].integer.value;  in decode_type0_hpx_record()
139 		hpx->t0->enable_serr     = fields[4].integer.value;  in decode_type0_hpx_record()
140 		hpx->t0->enable_perr     = fields[5].integer.value;  in decode_type0_hpx_record()
156 	u32 revision = fields[1].integer.value;  in decode_type1_hpx_record()
167 		hpx->t1->max_mem_read  = fields[2].integer.value;  in decode_type1_hpx_record()
168 		hpx->t1->avg_max_split = fields[3].integer.value;  in decode_type1_hpx_record()
169 		hpx->t1->tot_max_split = fields[4].integer.value;  in decode_type1_hpx_record()
185 	u32 revision = fields[1].integer.value;  in decode_type2_hpx_record()
196 		hpx->t2->unc_err_mask_and      = fields[2].integer.value;  in decode_type2_hpx_record()
197 		hpx->t2->unc_err_mask_or       = fields[3].integer.value;  in decode_type2_hpx_record()
198 		hpx->t2->unc_err_sever_and     = fields[4].integer.value;  in decode_type2_hpx_record()
199 		hpx->t2->unc_err_sever_or      = fields[5].integer.value;  in decode_type2_hpx_record()
200 		hpx->t2->cor_err_mask_and      = fields[6].integer.value;  in decode_type2_hpx_record()
201 		hpx->t2->cor_err_mask_or       = fields[7].integer.value;  in decode_type2_hpx_record()
202 		hpx->t2->adv_err_cap_and       = fields[8].integer.value;  in decode_type2_hpx_record()
203 		hpx->t2->adv_err_cap_or        = fields[9].integer.value;  in decode_type2_hpx_record()
204 		hpx->t2->pci_exp_devctl_and    = fields[10].integer.value;  in decode_type2_hpx_record()
205 		hpx->t2->pci_exp_devctl_or     = fields[11].integer.value;  in decode_type2_hpx_record()
206 		hpx->t2->pci_exp_lnkctl_and    = fields[12].integer.value;  in decode_type2_hpx_record()
207 		hpx->t2->pci_exp_lnkctl_or     = fields[13].integer.value;  in decode_type2_hpx_record()
208 		hpx->t2->sec_unc_err_sever_and = fields[14].integer.value;  in decode_type2_hpx_record()
209 		hpx->t2->sec_unc_err_sever_or  = fields[15].integer.value;  in decode_type2_hpx_record()
210 		hpx->t2->sec_unc_err_mask_and  = fields[16].integer.value;  in decode_type2_hpx_record()
211 		hpx->t2->sec_unc_err_mask_or   = fields[17].integer.value;  in decode_type2_hpx_record()
257 		type = fields[0].integer.value;  in acpi_run_hpx()
316 	hpp->t0->cache_line_size = fields[0].integer.value;  in acpi_run_hpp()
317 	hpp->t0->latency_timer   = fields[1].integer.value;  in acpi_run_hpp()
318 	hpp->t0->enable_serr     = fields[2].integer.value;  in acpi_run_hpp()
319 	hpp->t0->enable_perr     = fields[3].integer.value;  in acpi_run_hpp()
669 	if (obj->type == ACPI_TYPE_INTEGER && obj->integer.value == 1) {  in acpi_pci_add_bus()
737 			value = (int)elements[0].integer.value / 1000;  in pci_acpi_optimize_delay()
742 			value = (int)elements[3].integer.value / 1000;  in pci_acpi_optimize_delay()