Lines Matching refs:bar_sz
1284 u8 bar_sz; in xeon_setup_b2b_mw() local
1323 pci_read_config_byte(pdev, XEON_PBAR23SZ_OFFSET, &bar_sz); in xeon_setup_b2b_mw()
1324 dev_dbg(&pdev->dev, "PBAR23SZ %#x\n", bar_sz); in xeon_setup_b2b_mw()
1327 bar_sz -= 1; in xeon_setup_b2b_mw()
1329 bar_sz = 0; in xeon_setup_b2b_mw()
1331 pci_write_config_byte(pdev, XEON_SBAR23SZ_OFFSET, bar_sz); in xeon_setup_b2b_mw()
1332 pci_read_config_byte(pdev, XEON_SBAR23SZ_OFFSET, &bar_sz); in xeon_setup_b2b_mw()
1333 dev_dbg(&pdev->dev, "SBAR23SZ %#x\n", bar_sz); in xeon_setup_b2b_mw()
1336 pci_read_config_byte(pdev, XEON_PBAR45SZ_OFFSET, &bar_sz); in xeon_setup_b2b_mw()
1337 dev_dbg(&pdev->dev, "PBAR45SZ %#x\n", bar_sz); in xeon_setup_b2b_mw()
1340 bar_sz -= 1; in xeon_setup_b2b_mw()
1342 bar_sz = 0; in xeon_setup_b2b_mw()
1344 pci_write_config_byte(pdev, XEON_SBAR45SZ_OFFSET, bar_sz); in xeon_setup_b2b_mw()
1345 pci_read_config_byte(pdev, XEON_SBAR45SZ_OFFSET, &bar_sz); in xeon_setup_b2b_mw()
1346 dev_dbg(&pdev->dev, "SBAR45SZ %#x\n", bar_sz); in xeon_setup_b2b_mw()
1348 pci_read_config_byte(pdev, XEON_PBAR4SZ_OFFSET, &bar_sz); in xeon_setup_b2b_mw()
1349 dev_dbg(&pdev->dev, "PBAR4SZ %#x\n", bar_sz); in xeon_setup_b2b_mw()
1352 bar_sz -= 1; in xeon_setup_b2b_mw()
1354 bar_sz = 0; in xeon_setup_b2b_mw()
1356 pci_write_config_byte(pdev, XEON_SBAR4SZ_OFFSET, bar_sz); in xeon_setup_b2b_mw()
1357 pci_read_config_byte(pdev, XEON_SBAR4SZ_OFFSET, &bar_sz); in xeon_setup_b2b_mw()
1358 dev_dbg(&pdev->dev, "SBAR4SZ %#x\n", bar_sz); in xeon_setup_b2b_mw()
1360 pci_read_config_byte(pdev, XEON_PBAR5SZ_OFFSET, &bar_sz); in xeon_setup_b2b_mw()
1361 dev_dbg(&pdev->dev, "PBAR5SZ %#x\n", bar_sz); in xeon_setup_b2b_mw()
1364 bar_sz -= 1; in xeon_setup_b2b_mw()
1366 bar_sz = 0; in xeon_setup_b2b_mw()
1368 pci_write_config_byte(pdev, XEON_SBAR5SZ_OFFSET, bar_sz); in xeon_setup_b2b_mw()
1369 pci_read_config_byte(pdev, XEON_SBAR5SZ_OFFSET, &bar_sz); in xeon_setup_b2b_mw()
1370 dev_dbg(&pdev->dev, "SBAR5SZ %#x\n", bar_sz); in xeon_setup_b2b_mw()