Lines Matching defs:rtl_phy

1330 struct rtl_phy {  struct
1331 	struct bb_reg_def phyreg_def[4];	/*Radio A/B/C/D */
1332 	struct init_gain initgain_backup;
1333 	enum io_type current_io_type;
1335 	u8 rf_mode;
1336 	u8 rf_type;
1337 	u8 current_chan_bw;
1338 	u8 set_bwmode_inprogress;
1339 	u8 sw_chnl_inprogress;
1340 	u8 sw_chnl_stage;
1341 	u8 sw_chnl_step;
1342 	u8 current_channel;
1343 	u8 h2c_box_num;
1344 	u8 set_io_inprogress;
1345 	u8 lck_inprogress;
1348 	s32 reg_e94;
1349 	s32 reg_e9c;
1350 	s32 reg_ea4;
1351 	s32 reg_eac;
1352 	s32 reg_eb4;
1353 	s32 reg_ebc;
1354 	s32 reg_ec4;
1355 	s32 reg_ecc;
1356 	u8 rfpienable;
1357 	u8 reserve_0;
1358 	u16 reserve_1;
1359 	u32 reg_c04, reg_c08, reg_874;
1360 	u32 adda_backup[16];
1361 	u32 iqk_mac_backup[IQK_MAC_REG_NUM];
1362 	u32 iqk_bb_backup[10];
1363 	bool iqk_initialized;
1365 	bool rfpath_rx_enable[MAX_RF_PATH];
1366 	u8 reg_837;
1368 	bool need_iqk;
1369 	struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
1371 	bool rfpi_enable;
1372 	bool iqk_in_progress;
1374 	u8 pwrgroup_cnt;
1375 	u8 cck_high_power;
1377 	u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
1379 	u32 mcs_offset[MAX_PG_GROUP][16];
1380 	u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND]
1384 	u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
1387 	u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF]
1390 	u8 default_initialgain[4];
1393 	u8 cur_cck_txpwridx;
1394 	u8 cur_ofdm24g_txpwridx;
1395 	u8 cur_bw20_txpwridx;
1396 	u8 cur_bw40_txpwridx;
1398 	s8 txpwr_limit_2_4g[MAX_REGULATION_NUM]
1403 	s8 txpwr_limit_5g[MAX_REGULATION_NUM]
1409 	u32 rfreg_chnlval[2];
1410 	bool apk_done;
1411 	u32 reg_rf3c[2];	/* pathA / pathB  */
1413 	u32 backup_rf_0x1a;/*92ee*/
1415 	u8 framesync;
1416 	u32 framesync_c34;
1418 	u8 num_total_rfpath;
1419 	struct phy_parameters hwparam_tables[MAX_TAB];
1420 	u16 rf_pathmap;
1422 	u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1423 	enum rt_polarity_ctl polarity_ctl;