296 		rtl_set_bbreg(hw, addr, MASKDWORD, data);  in _rtl8723be_config_bb_reg()
820 					      MASKDWORD);  in rtl8723be_phy_get_hw_reg_originalvalue()
1475 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_iqk()
1477 	rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_iqk()
1487 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);  in _rtl8723be_phy_path_a_iqk()
1488 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl8723be_phy_path_a_iqk()
1490 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);  in _rtl8723be_phy_path_a_iqk()
1491 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_a_iqk()
1492 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_a_iqk()
1493 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_a_iqk()
1495 	rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x821403ea);  in _rtl8723be_phy_path_a_iqk()
1496 	rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160000);  in _rtl8723be_phy_path_a_iqk()
1497 	rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);  in _rtl8723be_phy_path_a_iqk()
1498 	rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);  in _rtl8723be_phy_path_a_iqk()
1500 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911);  in _rtl8723be_phy_path_a_iqk()
1502 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl8723be_phy_path_a_iqk()
1505 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);  in _rtl8723be_phy_path_a_iqk()
1506 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl8723be_phy_path_a_iqk()
1511 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_iqk()
1514 	reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);  in _rtl8723be_phy_path_a_iqk()
1515 	reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);  in _rtl8723be_phy_path_a_iqk()
1516 	reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);  in _rtl8723be_phy_path_a_iqk()
1548 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_rx_iqk()
1551 	rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_rx_iqk()
1560 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl8723be_phy_path_a_rx_iqk()
1563 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);  in _rtl8723be_phy_path_a_rx_iqk()
1564 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl8723be_phy_path_a_rx_iqk()
1567 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);  in _rtl8723be_phy_path_a_rx_iqk()
1568 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_a_rx_iqk()
1569 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_a_rx_iqk()
1570 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_a_rx_iqk()
1572 	rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160ff0);  in _rtl8723be_phy_path_a_rx_iqk()
1573 	rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000);  in _rtl8723be_phy_path_a_rx_iqk()
1574 	rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);  in _rtl8723be_phy_path_a_rx_iqk()
1575 	rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);  in _rtl8723be_phy_path_a_rx_iqk()
1578 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);  in _rtl8723be_phy_path_a_rx_iqk()
1581 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl8723be_phy_path_a_rx_iqk()
1584 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);  in _rtl8723be_phy_path_a_rx_iqk()
1585 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl8723be_phy_path_a_rx_iqk()
1590 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_rx_iqk()
1593 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl8723be_phy_path_a_rx_iqk()
1594 	reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);  in _rtl8723be_phy_path_a_rx_iqk()
1595 	reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);  in _rtl8723be_phy_path_a_rx_iqk()
1619 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32tmp);  in _rtl8723be_phy_path_a_rx_iqk()
1623 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_rx_iqk()
1635 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl8723be_phy_path_a_rx_iqk()
1638 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_a_rx_iqk()
1639 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c);  in _rtl8723be_phy_path_a_rx_iqk()
1640 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_a_rx_iqk()
1641 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_a_rx_iqk()
1643 	rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82110000);  in _rtl8723be_phy_path_a_rx_iqk()
1644 	rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x2816001f);  in _rtl8723be_phy_path_a_rx_iqk()
1645 	rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);  in _rtl8723be_phy_path_a_rx_iqk()
1646 	rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);  in _rtl8723be_phy_path_a_rx_iqk()
1649 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a8d1);  in _rtl8723be_phy_path_a_rx_iqk()
1652 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl8723be_phy_path_a_rx_iqk()
1655 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);  in _rtl8723be_phy_path_a_rx_iqk()
1656 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl8723be_phy_path_a_rx_iqk()
1661 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_rx_iqk()
1664 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl8723be_phy_path_a_rx_iqk()
1665 	reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD);  in _rtl8723be_phy_path_a_rx_iqk()
1668 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_rx_iqk()
1695 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_b_iqk()
1697 	rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000280);  in _rtl8723be_phy_path_b_iqk()
1705 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);  in _rtl8723be_phy_path_b_iqk()
1706 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl8723be_phy_path_b_iqk()
1708 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);  in _rtl8723be_phy_path_b_iqk()
1709 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_b_iqk()
1710 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_b_iqk()
1711 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_b_iqk()
1713 	rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x821403ea);  in _rtl8723be_phy_path_b_iqk()
1714 	rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000);  in _rtl8723be_phy_path_b_iqk()
1715 	rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);  in _rtl8723be_phy_path_b_iqk()
1716 	rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);  in _rtl8723be_phy_path_b_iqk()
1719 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911);  in _rtl8723be_phy_path_b_iqk()
1722 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl8723be_phy_path_b_iqk()
1725 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);  in _rtl8723be_phy_path_b_iqk()
1726 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl8723be_phy_path_b_iqk()
1731 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_b_iqk()
1734 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl8723be_phy_path_b_iqk()
1735 	reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);  in _rtl8723be_phy_path_b_iqk()
1736 	reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);  in _rtl8723be_phy_path_b_iqk()
1768 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_b_rx_iqk()
1770 	rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000280);  in _rtl8723be_phy_path_b_rx_iqk()
1784 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);  in _rtl8723be_phy_path_b_rx_iqk()
1785 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl8723be_phy_path_b_rx_iqk()
1788 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);  in _rtl8723be_phy_path_b_rx_iqk()
1789 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_b_rx_iqk()
1790 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_b_rx_iqk()
1791 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_b_rx_iqk()
1793 	rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160ff0);  in _rtl8723be_phy_path_b_rx_iqk()
1794 	rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000);  in _rtl8723be_phy_path_b_rx_iqk()
1795 	rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);  in _rtl8723be_phy_path_b_rx_iqk()
1796 	rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);  in _rtl8723be_phy_path_b_rx_iqk()
1799 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);  in _rtl8723be_phy_path_b_rx_iqk()
1801 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl8723be_phy_path_b_rx_iqk()
1804 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);  in _rtl8723be_phy_path_b_rx_iqk()
1805 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl8723be_phy_path_b_rx_iqk()
1810 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_b_rx_iqk()
1812 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl8723be_phy_path_b_rx_iqk()
1813 	reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);  in _rtl8723be_phy_path_b_rx_iqk()
1814 	reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);  in _rtl8723be_phy_path_b_rx_iqk()
1838 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32tmp);  in _rtl8723be_phy_path_b_rx_iqk()
1843 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_b_rx_iqk()
1855 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl8723be_phy_path_b_rx_iqk()
1858 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_b_rx_iqk()
1859 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c);  in _rtl8723be_phy_path_b_rx_iqk()
1860 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_b_rx_iqk()
1861 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_b_rx_iqk()
1863 	rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82110000);  in _rtl8723be_phy_path_b_rx_iqk()
1864 	rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x2816001f);  in _rtl8723be_phy_path_b_rx_iqk()
1865 	rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);  in _rtl8723be_phy_path_b_rx_iqk()
1866 	rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);  in _rtl8723be_phy_path_b_rx_iqk()
1869 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a8d1);  in _rtl8723be_phy_path_b_rx_iqk()
1871 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl8723be_phy_path_b_rx_iqk()
1874 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);  in _rtl8723be_phy_path_b_rx_iqk()
1875 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl8723be_phy_path_b_rx_iqk()
1880 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_b_rx_iqk()
1882 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl8723be_phy_path_b_rx_iqk()
1883 	reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD);  in _rtl8723be_phy_path_b_rx_iqk()
1919 					  MASKDWORD) >> 22) & 0x3FF;  in _rtl8723be_phy_path_b_fill_iqk_matrix()
2071 	path_sel_bb = rtl_get_bbreg(hw, 0x948, MASKDWORD);  in _rtl8723be_phy_iq_calibrate()
2077 	rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);  in _rtl8723be_phy_iq_calibrate()
2078 	rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);  in _rtl8723be_phy_iq_calibrate()
2079 	rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);  in _rtl8723be_phy_iq_calibrate()
2087 			result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &  in _rtl8723be_phy_iq_calibrate()
2089 			result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &  in _rtl8723be_phy_iq_calibrate()
2103 			result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &  in _rtl8723be_phy_iq_calibrate()
2105 			result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &  in _rtl8723be_phy_iq_calibrate()
2124 							      MASKDWORD) &  in _rtl8723be_phy_iq_calibrate()
2127 							      MASKDWORD) &  in _rtl8723be_phy_iq_calibrate()
2141 							      MASKDWORD) &  in _rtl8723be_phy_iq_calibrate()
2144 							      MASKDWORD) &  in _rtl8723be_phy_iq_calibrate()
2154 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0);  in _rtl8723be_phy_iq_calibrate()
2165 		rtl_set_bbreg(hw, 0x948, MASKDWORD, path_sel_bb);  in _rtl8723be_phy_iq_calibrate()
2174 		rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00);  in _rtl8723be_phy_iq_calibrate()
2175 		rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00);  in _rtl8723be_phy_iq_calibrate()
2261 		rtl_set_bbreg(hw, 0x92C, MASKDWORD, 0x1);  in _rtl8723be_phy_set_rfpath_switch()
2263 		rtl_set_bbreg(hw, 0x92C, MASKDWORD, 0x2);  in _rtl8723be_phy_set_rfpath_switch()
2305 	path_sel_bb = rtl_get_bbreg(hw, 0x948, MASKDWORD);  in rtl8723be_phy_iq_calibrate()
2407 	rtl_set_bbreg(hw, 0x948, MASKDWORD, path_sel_bb);  in rtl8723be_phy_iq_calibrate()