Lines Matching refs:MASKDWORD
243 if (bitmask != MASKDWORD) { in rtl92d_phy_set_bb_reg()
276 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); in _rtl92d_phy_rf_serial_read()
280 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); in _rtl92d_phy_rf_serial_read()
283 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, in _rtl92d_phy_rf_serial_read()
286 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); in _rtl92d_phy_rf_serial_read()
289 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, in _rtl92d_phy_rf_serial_read()
322 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); in _rtl92d_phy_rf_serial_write()
569 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, in _rtl92d_phy_config_bb_with_headerfile()
581 MASKDWORD, in _rtl92d_phy_config_bb_with_headerfile()
597 MASKDWORD, in _rtl92d_phy_config_bb_with_headerfile()
613 MASKDWORD, in _rtl92d_phy_config_bb_with_headerfile()
864 MASKDWORD); in rtl92d_phy_get_hw_reg_originalvalue()
1422 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f); in _rtl92d_phy_patha_iqk()
1423 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f); in _rtl92d_phy_patha_iqk()
1425 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1426 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1428 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102); in _rtl92d_phy_patha_iqk()
1429 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160206); in _rtl92d_phy_patha_iqk()
1432 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1433 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1434 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102); in _rtl92d_phy_patha_iqk()
1435 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160206); in _rtl92d_phy_patha_iqk()
1439 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl92d_phy_patha_iqk()
1442 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); in _rtl92d_phy_patha_iqk()
1443 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92d_phy_patha_iqk()
1450 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92d_phy_patha_iqk()
1452 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); in _rtl92d_phy_patha_iqk()
1454 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); in _rtl92d_phy_patha_iqk()
1456 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); in _rtl92d_phy_patha_iqk()
1492 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); in _rtl92d_phy_patha_iqk_5g_normal()
1493 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); in _rtl92d_phy_patha_iqk_5g_normal()
1494 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140307); in _rtl92d_phy_patha_iqk_5g_normal()
1495 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68160960); in _rtl92d_phy_patha_iqk_5g_normal()
1498 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); in _rtl92d_phy_patha_iqk_5g_normal()
1499 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); in _rtl92d_phy_patha_iqk_5g_normal()
1500 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82110000); in _rtl92d_phy_patha_iqk_5g_normal()
1501 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68110000); in _rtl92d_phy_patha_iqk_5g_normal()
1505 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl92d_phy_patha_iqk_5g_normal()
1507 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60); in _rtl92d_phy_patha_iqk_5g_normal()
1508 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30); in _rtl92d_phy_patha_iqk_5g_normal()
1513 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); in _rtl92d_phy_patha_iqk_5g_normal()
1514 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92d_phy_patha_iqk_5g_normal()
1521 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92d_phy_patha_iqk_5g_normal()
1523 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); in _rtl92d_phy_patha_iqk_5g_normal()
1525 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); in _rtl92d_phy_patha_iqk_5g_normal()
1527 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); in _rtl92d_phy_patha_iqk_5g_normal()
1549 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, in _rtl92d_phy_patha_iqk_5g_normal()
1551 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, in _rtl92d_phy_patha_iqk_5g_normal()
1566 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); in _rtl92d_phy_pathb_iqk()
1567 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); in _rtl92d_phy_pathb_iqk()
1573 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1575 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1577 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1579 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1581 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1609 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); in _rtl92d_phy_pathb_iqk_5g_normal()
1610 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); in _rtl92d_phy_pathb_iqk_5g_normal()
1611 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82110000); in _rtl92d_phy_pathb_iqk_5g_normal()
1612 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68110000); in _rtl92d_phy_pathb_iqk_5g_normal()
1615 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); in _rtl92d_phy_pathb_iqk_5g_normal()
1616 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); in _rtl92d_phy_pathb_iqk_5g_normal()
1617 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140307); in _rtl92d_phy_pathb_iqk_5g_normal()
1618 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68160960); in _rtl92d_phy_pathb_iqk_5g_normal()
1622 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl92d_phy_pathb_iqk_5g_normal()
1625 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700); in _rtl92d_phy_pathb_iqk_5g_normal()
1626 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30); in _rtl92d_phy_pathb_iqk_5g_normal()
1632 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xfa000000); in _rtl92d_phy_pathb_iqk_5g_normal()
1633 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92d_phy_pathb_iqk_5g_normal()
1641 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1643 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1645 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1647 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1649 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1667 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, in _rtl92d_phy_pathb_iqk_5g_normal()
1669 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, in _rtl92d_phy_pathb_iqk_5g_normal()
1683 adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], MASKDWORD); in _rtl92d_phy_save_adda_registers()
1708 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, adda_backup[i]); in _rtl92d_phy_reload_adda_registers()
1736 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, pathon); in _rtl92d_phy_path_adda_on()
1759 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); in _rtl92d_phy_patha_standby()
1760 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000); in _rtl92d_phy_patha_standby()
1761 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92d_phy_patha_standby()
1772 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); in _rtl92d_phy_pimode_switch()
1773 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); in _rtl92d_phy_pimode_switch()
1804 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD); in _rtl92d_phy_iq_calibrate()
1827 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); in _rtl92d_phy_iq_calibrate()
1828 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); in _rtl92d_phy_iq_calibrate()
1829 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000); in _rtl92d_phy_iq_calibrate()
1832 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, in _rtl92d_phy_iq_calibrate()
1834 rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, MASKDWORD, in _rtl92d_phy_iq_calibrate()
1841 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate()
1843 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate()
1846 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92d_phy_iq_calibrate()
1847 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); in _rtl92d_phy_iq_calibrate()
1848 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); in _rtl92d_phy_iq_calibrate()
1854 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1856 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1858 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1860 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1868 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1870 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1886 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1888 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1890 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1892 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1899 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1901 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1913 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); in _rtl92d_phy_iq_calibrate()
1933 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00); in _rtl92d_phy_iq_calibrate()
1934 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00); in _rtl92d_phy_iq_calibrate()
1971 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD); in _rtl92d_phy_iq_calibrate_5g_normal()
2001 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); in _rtl92d_phy_iq_calibrate_5g_normal()
2002 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); in _rtl92d_phy_iq_calibrate_5g_normal()
2003 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000); in _rtl92d_phy_iq_calibrate_5g_normal()
2007 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate_5g_normal()
2009 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate_5g_normal()
2012 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92d_phy_iq_calibrate_5g_normal()
2013 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x10007c00); in _rtl92d_phy_iq_calibrate_5g_normal()
2014 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); in _rtl92d_phy_iq_calibrate_5g_normal()
2018 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2020 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2022 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2024 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2030 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2032 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2045 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2047 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2049 result[t][6] = (rtl_get_bbreg(hw, 0xec4, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2051 result[t][7] = (rtl_get_bbreg(hw, 0xecc, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2056 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2058 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2069 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); in _rtl92d_phy_iq_calibrate_5g_normal()
2169 MASKDWORD) >> 22) & 0x3FF; /* OFDM0_D */ in _rtl92d_phy_patha_fill_iqk_matrix()
2200 MASKDWORD)); in _rtl92d_phy_patha_fill_iqk_matrix()
2228 MASKDWORD) >> 22) & 0x3FF; in _rtl92d_phy_pathb_fill_iqk_matrix()
2882 MASKDWORD); in rtl92d_phy_sw_chnl()
3390 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
3392 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
3446 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
3449 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
3452 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
3455 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
3482 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100); in rtl92d_update_bbrf_configuration()
3483 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100); in rtl92d_update_bbrf_configuration()