Lines Matching refs:rtlpriv
44 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_read_dword_dbi() local
47 rtl_write_word(rtlpriv, REG_DBI_CTRL, (offset & 0xFFC)); in rtl92de_read_dword_dbi()
48 rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(1) | direct); in rtl92de_read_dword_dbi()
50 value = rtl_read_dword(rtlpriv, REG_DBI_RDATA); in rtl92de_read_dword_dbi()
57 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_write_dword_dbi() local
59 rtl_write_word(rtlpriv, REG_DBI_CTRL, ((offset & 0xFFC) | 0xF000)); in rtl92de_write_dword_dbi()
60 rtl_write_dword(rtlpriv, REG_DBI_WDATA, value); in rtl92de_write_dword_dbi()
61 rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(0) | direct); in rtl92de_write_dword_dbi()
68 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_set_bcn_ctrl_reg() local
72 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val); in _rtl92de_set_bcn_ctrl_reg()
77 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_stop_tx_beacon() local
80 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); in _rtl92de_stop_tx_beacon()
81 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); in _rtl92de_stop_tx_beacon()
82 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff); in _rtl92de_stop_tx_beacon()
83 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); in _rtl92de_stop_tx_beacon()
84 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); in _rtl92de_stop_tx_beacon()
86 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); in _rtl92de_stop_tx_beacon()
91 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_resume_tx_beacon() local
94 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); in _rtl92de_resume_tx_beacon()
95 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); in _rtl92de_resume_tx_beacon()
96 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a); in _rtl92de_resume_tx_beacon()
97 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); in _rtl92de_resume_tx_beacon()
98 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); in _rtl92de_resume_tx_beacon()
100 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); in _rtl92de_resume_tx_beacon()
115 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_get_hw_reg() local
130 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, in rtl92de_get_hw_reg()
135 val_rcr = rtl_read_dword(rtlpriv, REG_RCR); in rtl92de_get_hw_reg()
152 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); in rtl92de_get_hw_reg()
153 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); in rtl92de_get_hw_reg()
158 *((bool *)(val)) = rtlpriv->dm.interrupt_migration; in rtl92de_get_hw_reg()
161 *((bool *)(val)) = rtlpriv->dm.disable_tx_int; in rtl92de_get_hw_reg()
173 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_set_hw_reg() local
184 rtl_write_byte(rtlpriv, (REG_MACID + idx), in rtl92de_set_hw_reg()
196 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff); in rtl92de_set_hw_reg()
197 rtl_write_byte(rtlpriv, REG_RRSR + 1, in rtl92de_set_hw_reg()
204 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, in rtl92de_set_hw_reg()
210 rtl_write_byte(rtlpriv, (REG_BSSID + idx), in rtl92de_set_hw_reg()
215 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); in rtl92de_set_hw_reg()
216 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); in rtl92de_set_hw_reg()
217 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); in rtl92de_set_hw_reg()
218 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); in rtl92de_set_hw_reg()
220 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, in rtl92de_set_hw_reg()
223 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, in rtl92de_set_hw_reg()
229 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, in rtl92de_set_hw_reg()
231 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); in rtl92de_set_hw_reg()
233 rtlpriv->cfg->ops->set_hw_reg(hw, in rtl92de_set_hw_reg()
245 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp); in rtl92de_set_hw_reg()
260 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, in rtl92de_set_hw_reg()
263 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, in rtl92de_set_hw_reg()
272 mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg; in rtl92de_set_hw_reg()
274 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, in rtl92de_set_hw_reg()
277 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, in rtl92de_set_hw_reg()
308 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, regtoSet); in rtl92de_set_hw_reg()
309 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, in rtl92de_set_hw_reg()
319 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL, in rtl92de_set_hw_reg()
328 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL); in rtl92de_set_hw_reg()
343 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, in rtl92de_set_hw_reg()
365 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE, in rtl92de_set_hw_reg()
368 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl); in rtl92de_set_hw_reg()
372 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]); in rtl92de_set_hw_reg()
378 rtl_write_word(rtlpriv, REG_RL, in rtl92de_set_hw_reg()
384 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); in rtl92de_set_hw_reg()
396 rtl_write_byte(rtlpriv, REG_SECCFG, *val); in rtl92de_set_hw_reg()
412 rtlpriv->cfg->ops->set_hw_reg(hw, in rtl92de_set_hw_reg()
414 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); in rtl92de_set_hw_reg()
415 rtl_write_byte(rtlpriv, REG_CR + 1, in rtl92de_set_hw_reg()
419 tmp_reg422 = rtl_read_byte(rtlpriv, in rtl92de_set_hw_reg()
423 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, in rtl92de_set_hw_reg()
429 rtl_write_byte(rtlpriv, in rtl92de_set_hw_reg()
432 rtl_write_byte(rtlpriv, REG_CR + 1, in rtl92de_set_hw_reg()
440 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); in rtl92de_set_hw_reg()
442 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp | in rtl92de_set_hw_reg()
452 rtl_write_dword(rtlpriv, REG_TSFTR, in rtl92de_set_hw_reg()
454 rtl_write_dword(rtlpriv, REG_TSFTR + 4, in rtl92de_set_hw_reg()
470 rtl_write_dword(rtlpriv, REG_INT_MIG, 0xfe000fa0); in rtl92de_set_hw_reg()
471 rtlpriv->dm.interrupt_migration = int_migration; in rtl92de_set_hw_reg()
474 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); in rtl92de_set_hw_reg()
475 rtlpriv->dm.interrupt_migration = int_migration; in rtl92de_set_hw_reg()
489 rtlpriv->cfg->ops->update_interrupt_mask(hw, 0, in rtl92de_set_hw_reg()
491 rtlpriv->dm.disable_tx_int = disable_ac_int; in rtl92de_set_hw_reg()
494 rtlpriv->cfg->ops->update_interrupt_mask(hw, in rtl92de_set_hw_reg()
496 rtlpriv->dm.disable_tx_int = disable_ac_int; in rtl92de_set_hw_reg()
508 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_llt_write() local
514 rtl_write_dword(rtlpriv, REG_LLT_INIT, value); in _rtl92de_llt_write()
516 value = rtl_read_dword(rtlpriv, REG_LLT_INIT); in _rtl92de_llt_write()
531 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_llt_table_init() local
539 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) { in _rtl92de_llt_table_init()
554 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8); in _rtl92de_llt_table_init()
555 rtl_write_dword(rtlpriv, REG_RQPN, value32); in _rtl92de_llt_table_init()
559 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, in _rtl92de_llt_table_init()
560 (rtl_read_word(rtlpriv, REG_TRXFF_BNDY + 2) << 16 | in _rtl92de_llt_table_init()
565 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy); in _rtl92de_llt_table_init()
569 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); in _rtl92de_llt_table_init()
570 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); in _rtl92de_llt_table_init()
574 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy); in _rtl92de_llt_table_init()
580 rtl_write_byte(rtlpriv, REG_PBP, 0x11); in _rtl92de_llt_table_init()
583 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); in _rtl92de_llt_table_init()
617 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_gen_refresh_led_state() local
620 struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0; in _rtl92de_gen_refresh_led_state()
634 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_init_mac() local
645 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); in _rtl92de_init_mac()
646 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x05); in _rtl92de_init_mac()
654 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); in _rtl92de_init_mac()
657 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F); in _rtl92de_init_mac()
664 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0); in _rtl92de_init_mac()
666 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp); in _rtl92de_init_mac()
670 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1); in _rtl92de_init_mac()
675 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1); in _rtl92de_init_mac()
681 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012); in _rtl92de_init_mac()
686 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82); in _rtl92de_init_mac()
693 rtl_write_word(rtlpriv, REG_CR, 0x0); in _rtl92de_init_mac()
696 rtl_write_word(rtlpriv, REG_CR, 0x2ff); in _rtl92de_init_mac()
699 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x0); in _rtl92de_init_mac()
711 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); in _rtl92de_init_mac()
712 rtl_write_byte(rtlpriv, REG_HISRE, 0xff); in _rtl92de_init_mac()
730 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL); in _rtl92de_init_mac()
733 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp); in _rtl92de_init_mac()
738 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F); in _rtl92de_init_mac()
745 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); in _rtl92de_init_mac()
749 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config); in _rtl92de_init_mac()
752 rtl_write_byte(rtlpriv, 0x4d0, 0x0); in _rtl92de_init_mac()
755 rtl_write_dword(rtlpriv, REG_BCNQ_DESA, in _rtl92de_init_mac()
757 rtl_write_dword(rtlpriv, REG_MGQ_DESA, rtlpci->tx_ring[MGNT_QUEUE].dma); in _rtl92de_init_mac()
758 rtl_write_dword(rtlpriv, REG_VOQ_DESA, rtlpci->tx_ring[VO_QUEUE].dma); in _rtl92de_init_mac()
759 rtl_write_dword(rtlpriv, REG_VIQ_DESA, rtlpci->tx_ring[VI_QUEUE].dma); in _rtl92de_init_mac()
760 rtl_write_dword(rtlpriv, REG_BEQ_DESA, rtlpci->tx_ring[BE_QUEUE].dma); in _rtl92de_init_mac()
761 rtl_write_dword(rtlpriv, REG_BKQ_DESA, rtlpci->tx_ring[BK_QUEUE].dma); in _rtl92de_init_mac()
762 rtl_write_dword(rtlpriv, REG_HQ_DESA, rtlpci->tx_ring[HIGH_QUEUE].dma); in _rtl92de_init_mac()
764 rtl_write_dword(rtlpriv, REG_RX_DESA, in _rtl92de_init_mac()
770 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x33); in _rtl92de_init_mac()
773 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); in _rtl92de_init_mac()
776 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); in _rtl92de_init_mac()
777 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6)); in _rtl92de_init_mac()
780 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); in _rtl92de_init_mac()
787 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0); in _rtl92de_init_mac()
795 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_hw_configure() local
801 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8); in _rtl92de_hw_configure()
802 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); in _rtl92de_hw_configure()
803 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr); in _rtl92de_hw_configure()
804 rtl_write_byte(rtlpriv, REG_SLOT, 0x09); in _rtl92de_hw_configure()
805 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0); in _rtl92de_hw_configure()
806 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80); in _rtl92de_hw_configure()
807 rtl_write_word(rtlpriv, REG_RL, 0x0707); in _rtl92de_hw_configure()
808 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802); in _rtl92de_hw_configure()
809 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF); in _rtl92de_hw_configure()
810 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000); in _rtl92de_hw_configure()
811 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504); in _rtl92de_hw_configure()
812 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000); in _rtl92de_hw_configure()
813 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504); in _rtl92de_hw_configure()
816 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb9726641); in _rtl92de_hw_configure()
818 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x66626641); in _rtl92de_hw_configure()
820 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841); in _rtl92de_hw_configure()
821 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2); in _rtl92de_hw_configure()
822 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a); in _rtl92de_hw_configure()
824 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val); in _rtl92de_hw_configure()
825 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); in _rtl92de_hw_configure()
826 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C); in _rtl92de_hw_configure()
827 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); in _rtl92de_hw_configure()
828 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); in _rtl92de_hw_configure()
830 rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0x6666); in _rtl92de_hw_configure()
832 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40); in _rtl92de_hw_configure()
834 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010); in _rtl92de_hw_configure()
835 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010); in _rtl92de_hw_configure()
837 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010); in _rtl92de_hw_configure()
839 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010); in _rtl92de_hw_configure()
841 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff); in _rtl92de_hw_configure()
842 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff); in _rtl92de_hw_configure()
843 switch (rtlpriv->phy.rf_type) { in _rtl92de_hw_configure()
857 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_enable_aspm_back_door() local
860 rtl_write_byte(rtlpriv, 0x34b, 0x93); in _rtl92de_enable_aspm_back_door()
861 rtl_write_word(rtlpriv, 0x350, 0x870c); in _rtl92de_enable_aspm_back_door()
862 rtl_write_byte(rtlpriv, 0x352, 0x1); in _rtl92de_enable_aspm_back_door()
864 rtl_write_byte(rtlpriv, 0x349, 0x1b); in _rtl92de_enable_aspm_back_door()
866 rtl_write_byte(rtlpriv, 0x349, 0x03); in _rtl92de_enable_aspm_back_door()
867 rtl_write_word(rtlpriv, 0x350, 0x2718); in _rtl92de_enable_aspm_back_door()
868 rtl_write_byte(rtlpriv, 0x352, 0x1); in _rtl92de_enable_aspm_back_door()
873 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_enable_hw_security_config() local
876 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, in rtl92de_enable_hw_security_config()
878 rtlpriv->sec.pairwise_enc_algorithm, in rtl92de_enable_hw_security_config()
879 rtlpriv->sec.group_enc_algorithm); in rtl92de_enable_hw_security_config()
880 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { in rtl92de_enable_hw_security_config()
881 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, in rtl92de_enable_hw_security_config()
886 if (rtlpriv->sec.use_defaultkey) { in rtl92de_enable_hw_security_config()
891 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); in rtl92de_enable_hw_security_config()
892 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, in rtl92de_enable_hw_security_config()
894 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); in rtl92de_enable_hw_security_config()
899 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_hw_init() local
902 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92de_hw_init()
927 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, in rtl92de_hw_init()
932 rtlpriv->psc.fw_current_inpsmode = false; in rtl92de_hw_init()
934 tmp_u1b = rtl_read_byte(rtlpriv, 0x605); in rtl92de_hw_init()
936 rtl_write_byte(rtlpriv, 0x605, tmp_u1b); in rtl92de_hw_init()
939 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, in rtl92de_hw_init()
942 tmp_u1b = rtl_read_byte(rtlpriv, 0x4d0); in rtl92de_hw_init()
944 rtl_write_byte(rtlpriv, 0x4d0, tmp_u1b); in rtl92de_hw_init()
946 rtl_write_byte(rtlpriv, 0x4d3, 0x80); in rtl92de_hw_init()
948 tmp_u1b = rtl_read_byte(rtlpriv, 0x605); in rtl92de_hw_init()
950 rtl_write_byte(rtlpriv, 0x605, tmp_u1b); in rtl92de_hw_init()
954 rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xff); in rtl92de_hw_init()
955 rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200); in rtl92de_hw_init()
956 rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05); in rtl92de_hw_init()
964 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR); in rtl92de_hw_init()
1015 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); in rtl92de_hw_init()
1051 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_read_chip_version() local
1055 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); in _rtl92de_read_chip_version()
1058 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "TEST CHIP!!!\n"); in _rtl92de_read_chip_version()
1061 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Normal CHIP!!!\n"); in _rtl92de_read_chip_version()
1069 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_set_media_status() local
1070 u8 bt_msr = rtl_read_byte(rtlpriv, MSR); in _rtl92de_set_media_status()
1085 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, in _rtl92de_set_media_status()
1089 bcnfunc_enable = rtl_read_byte(rtlpriv, REG_BCN_CTRL); in _rtl92de_set_media_status()
1095 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, in _rtl92de_set_media_status()
1101 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, in _rtl92de_set_media_status()
1108 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, in _rtl92de_set_media_status()
1114 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, in _rtl92de_set_media_status()
1121 rtl_write_byte(rtlpriv, MSR, bt_msr); in _rtl92de_set_media_status()
1122 rtlpriv->cfg->ops->led_control(hw, ledaction); in _rtl92de_set_media_status()
1124 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); in _rtl92de_set_media_status()
1126 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); in _rtl92de_set_media_status()
1132 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_set_check_bssid() local
1135 if (rtlpriv->psc.rfpwr_state != ERFON) in rtl92de_set_check_bssid()
1138 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); in rtl92de_set_check_bssid()
1142 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); in rtl92de_set_check_bssid()
1147 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); in rtl92de_set_check_bssid()
1153 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_set_network_type() local
1159 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { in rtl92de_set_network_type()
1174 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92d_linked_set_reg() local
1175 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92d_linked_set_reg()
1181 RT_TRACE(rtlpriv, COMP_SCAN | COMP_INIT, DBG_DMESG, in rtl92d_linked_set_reg()
1196 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_enable_interrupt() local
1199 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF); in rtl92de_enable_interrupt()
1200 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF); in rtl92de_enable_interrupt()
1205 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_disable_interrupt() local
1208 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED); in rtl92de_disable_interrupt()
1209 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED); in rtl92de_disable_interrupt()
1215 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_poweroff_adapter() local
1219 rtlpriv->intf_ops->enable_aspm(hw); in _rtl92de_poweroff_adapter()
1220 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); in _rtl92de_poweroff_adapter()
1225 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04); in _rtl92de_poweroff_adapter()
1231 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51); in _rtl92de_poweroff_adapter()
1234 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); in _rtl92de_poweroff_adapter()
1239 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000); in _rtl92de_poweroff_adapter()
1242 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL); in _rtl92de_poweroff_adapter()
1246 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, in _rtl92de_poweroff_adapter()
1250 rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790); in _rtl92de_poweroff_adapter()
1253 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080); in _rtl92de_poweroff_adapter()
1258 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80); in _rtl92de_poweroff_adapter()
1261 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23); in _rtl92de_poweroff_adapter()
1264 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e); in _rtl92de_poweroff_adapter()
1267 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e); in _rtl92de_poweroff_adapter()
1277 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10); in _rtl92de_poweroff_adapter()
1279 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, in _rtl92de_poweroff_adapter()
1281 REG_SPS0_CTRL, rtl_read_byte(rtlpriv, REG_SPS0_CTRL)); in _rtl92de_poweroff_adapter()
1286 if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) { in _rtl92de_poweroff_adapter()
1288 u1b_tmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS); in _rtl92de_poweroff_adapter()
1290 rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1b_tmp); in _rtl92de_poweroff_adapter()
1294 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<=======\n"); in _rtl92de_poweroff_adapter()
1299 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_card_disable() local
1311 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); in rtl92de_card_disable()
1321 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE); in rtl92de_card_disable()
1332 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); in rtl92de_card_disable()
1339 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in rtl92de_card_disable()
1343 if (rtlpriv->rtlhal.interfaceindex == 1) in rtl92de_card_disable()
1344 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0); in rtl92de_card_disable()
1349 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff); in rtl92de_card_disable()
1351 rtl_write_byte(rtlpriv, REG_CR, 0x0); in rtl92de_card_disable()
1352 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==> Do power off.......\n"); in rtl92de_card_disable()
1361 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_interrupt_recognized() local
1364 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; in rtl92de_interrupt_recognized()
1365 rtl_write_dword(rtlpriv, ISR, intvec->inta); in rtl92de_interrupt_recognized()
1370 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_set_beacon_related_registers() local
1377 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); in rtl92de_set_beacon_related_registers()
1378 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); in rtl92de_set_beacon_related_registers()
1379 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); in rtl92de_set_beacon_related_registers()
1380 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x20); in rtl92de_set_beacon_related_registers()
1381 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) in rtl92de_set_beacon_related_registers()
1382 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x30); in rtl92de_set_beacon_related_registers()
1384 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x20); in rtl92de_set_beacon_related_registers()
1385 rtl_write_byte(rtlpriv, 0x606, 0x30); in rtl92de_set_beacon_related_registers()
1390 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_set_beacon_interval() local
1394 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, in rtl92de_set_beacon_interval()
1397 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); in rtl92de_set_beacon_interval()
1404 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_update_interrupt_mask() local
1407 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n", in rtl92de_update_interrupt_mask()
1562 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_read_txpower_info() local
1578 if (IS_92D_D_CUT(rtlpriv->rtlhal.version) || in _rtl92de_read_txpower_info()
1579 IS_92D_E_CUT(rtlpriv->rtlhal.version)) { in _rtl92de_read_txpower_info()
1584 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, in _rtl92de_read_txpower_info()
1636 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, in _rtl92de_read_txpower_info()
1638 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, in _rtl92de_read_txpower_info()
1640 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, in _rtl92de_read_txpower_info()
1642 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, in _rtl92de_read_txpower_info()
1673 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_read_macphymode_from_prom() local
1679 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, in _rtl92de_read_macphymode_from_prom()
1683 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, in _rtl92de_read_macphymode_from_prom()
1698 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_efuse_update_chip_version() local
1699 enum version_8192d chipver = rtlpriv->rtlhal.version; in _rtl92de_efuse_update_chip_version()
1703 rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_H, in _rtl92de_efuse_update_chip_version()
1705 rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_L, in _rtl92de_efuse_update_chip_version()
1711 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "C-CUT!!!\n"); in _rtl92de_efuse_update_chip_version()
1715 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "D-CUT!!!\n"); in _rtl92de_efuse_update_chip_version()
1719 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "E-CUT!!!\n"); in _rtl92de_efuse_update_chip_version()
1726 rtlpriv->rtlhal.version = chipver; in _rtl92de_efuse_update_chip_version()
1731 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92de_read_adapter_info() local
1746 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) in _rtl92de_read_adapter_info()
1759 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, in _rtl92de_read_adapter_info()
1761 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr); in _rtl92de_read_adapter_info()
1786 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_read_eeprom_info() local
1792 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); in rtl92de_read_eeprom_info()
1795 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); in rtl92de_read_eeprom_info()
1798 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); in rtl92de_read_eeprom_info()
1802 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); in rtl92de_read_eeprom_info()
1815 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_update_hal_rate_table() local
1816 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92de_update_hal_rate_table()
1889 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); in rtl92de_update_hal_rate_table()
1890 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n", in rtl92de_update_hal_rate_table()
1891 rtl_read_dword(rtlpriv, REG_ARFR0)); in rtl92de_update_hal_rate_table()
1897 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_update_hal_rate_mask() local
1898 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92de_update_hal_rate_mask()
2022 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, in rtl92de_update_hal_rate_mask()
2033 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_update_hal_rate_tbl() local
2035 if (rtlpriv->dm.useramask) in rtl92de_update_hal_rate_tbl()
2043 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_update_channel_access_setting() local
2047 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, in rtl92de_update_channel_access_setting()
2053 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); in rtl92de_update_channel_access_setting()
2058 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_gpio_radio_on_off_checking() local
2070 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); in rtl92de_gpio_radio_on_off_checking()
2072 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); in rtl92de_gpio_radio_on_off_checking()
2076 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); in rtl92de_gpio_radio_on_off_checking()
2078 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv, in rtl92de_gpio_radio_on_off_checking()
2080 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL); in rtl92de_gpio_radio_on_off_checking()
2083 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, in rtl92de_gpio_radio_on_off_checking()
2089 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, in rtl92de_gpio_radio_on_off_checking()
2096 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); in rtl92de_gpio_radio_on_off_checking()
2098 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); in rtl92de_gpio_radio_on_off_checking()
2102 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); in rtl92de_gpio_radio_on_off_checking()
2104 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); in rtl92de_gpio_radio_on_off_checking()
2114 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_set_key() local
2134 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); in rtl92de_set_key()
2140 memset(rtlpriv->sec.key_buf[idx], 0, in rtl92de_set_key()
2142 rtlpriv->sec.key_len[idx] = 0; in rtl92de_set_key()
2165 if (is_wepkey || rtlpriv->sec.use_defaultkey) { in rtl92de_set_key()
2187 if (rtlpriv->sec.key_len[key_index] == 0) { in rtl92de_set_key()
2188 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, in rtl92de_set_key()
2195 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, in rtl92de_set_key()
2197 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]); in rtl92de_set_key()
2198 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, in rtl92de_set_key()
2200 rtlpriv->sec.key_buf[0][0], in rtl92de_set_key()
2201 rtlpriv->sec.key_buf[0][1]); in rtl92de_set_key()
2202 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, in rtl92de_set_key()
2205 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD, in rtl92de_set_key()
2207 rtlpriv->sec.pairwise_key, in rtl92de_set_key()
2208 rtlpriv-> in rtl92de_set_key()
2210 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, in rtl92de_set_key()
2215 rtlpriv-> in rtl92de_set_key()
2218 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, in rtl92de_set_key()
2226 rtlpriv->sec.key_buf[entry_id]); in rtl92de_set_key()
2231 rtlpriv->sec.key_buf in rtl92de_set_key()
2240 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_suspend() local
2242 rtlpriv->rtlhal.macphyctl_reg = rtl_read_byte(rtlpriv, in rtl92de_suspend()
2248 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92de_resume() local
2250 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL, in rtl92de_resume()
2251 rtlpriv->rtlhal.macphyctl_reg); in rtl92de_resume()