Lines Matching refs:rt2x00_set_field32
78 rt2x00_set_field32(®, PHY_CSR3_VALUE, value); in rt61pci_bbp_write()
79 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); in rt61pci_bbp_write()
80 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); in rt61pci_bbp_write()
81 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0); in rt61pci_bbp_write()
107 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); in rt61pci_bbp_read()
108 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); in rt61pci_bbp_read()
109 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1); in rt61pci_bbp_read()
136 rt2x00_set_field32(®, PHY_CSR4_VALUE, value); in rt61pci_rf_write()
137 rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, 21); in rt61pci_rf_write()
138 rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0); in rt61pci_rf_write()
139 rt2x00_set_field32(®, PHY_CSR4_BUSY, 1); in rt61pci_rf_write()
161 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); in rt61pci_mcu_request()
162 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); in rt61pci_mcu_request()
163 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); in rt61pci_mcu_request()
164 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); in rt61pci_mcu_request()
168 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); in rt61pci_mcu_request()
169 rt2x00_set_field32(®, HOST_CMD_CSR_INTERRUPT_MCU, 1); in rt61pci_mcu_request()
197 rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in); in rt61pci_eepromregister_write()
198 rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out); in rt61pci_eepromregister_write()
199 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, in rt61pci_eepromregister_write()
201 rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT, in rt61pci_eepromregister_write()
298 rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, *delay_on); in rt61pci_blink_set()
299 rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, *delay_off); in rt61pci_blink_set()
376 rt2x00_set_field32(®, field, crypto->cipher); in rt61pci_config_shared_key()
383 rt2x00_set_field32(®, field, crypto->cipher); in rt61pci_config_shared_key()
530 rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC, in rt61pci_config_filter()
532 rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL, in rt61pci_config_filter()
534 rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL, in rt61pci_config_filter()
536 rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME, in rt61pci_config_filter()
538 rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS, in rt61pci_config_filter()
541 rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1); in rt61pci_config_filter()
542 rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST, in rt61pci_config_filter()
544 rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0); in rt61pci_config_filter()
545 rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS, in rt61pci_config_filter()
562 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, conf->sync); in rt61pci_config_intf()
568 rt2x00_set_field32(®, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff); in rt61pci_config_intf()
577 rt2x00_set_field32(®, MAC_CSR5_BSS_ID_MASK, 3); in rt61pci_config_intf()
593 rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32); in rt61pci_config_erp()
594 rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER); in rt61pci_config_erp()
599 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1); in rt61pci_config_erp()
600 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE, in rt61pci_config_erp()
611 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, in rt61pci_config_erp()
618 rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, erp->slot_time); in rt61pci_config_erp()
622 rt2x00_set_field32(®, MAC_CSR8_SIFS, erp->sifs); in rt61pci_config_erp()
623 rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3); in rt61pci_config_erp()
624 rt2x00_set_field32(®, MAC_CSR8_EIFS, erp->eifs); in rt61pci_config_erp()
720 rt2x00_set_field32(®, MAC_CSR13_DIR4, 0); in rt61pci_config_antenna_2529_rx()
721 rt2x00_set_field32(®, MAC_CSR13_VAL4, p1); in rt61pci_config_antenna_2529_rx()
723 rt2x00_set_field32(®, MAC_CSR13_DIR3, 0); in rt61pci_config_antenna_2529_rx()
724 rt2x00_set_field32(®, MAC_CSR13_VAL3, !p2); in rt61pci_config_antenna_2529_rx()
827 rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG, in rt61pci_config_ant()
829 rt2x00_set_field32(®, PHY_CSR0_PA_PE_A, in rt61pci_config_ant()
876 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); in rt61pci_config_channel()
877 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); in rt61pci_config_channel()
933 rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1); in rt61pci_config_retry_limit()
934 rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_STEP, 0); in rt61pci_config_retry_limit()
935 rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0); in rt61pci_config_retry_limit()
936 rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, in rt61pci_config_retry_limit()
938 rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, in rt61pci_config_retry_limit()
953 rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, in rt61pci_config_ps()
955 rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, in rt61pci_config_ps()
957 rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 5); in rt61pci_config_ps()
960 rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0); in rt61pci_config_ps()
963 rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 1); in rt61pci_config_ps()
974 rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, 0); in rt61pci_config_ps()
975 rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0); in rt61pci_config_ps()
976 rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0); in rt61pci_config_ps()
977 rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 0); in rt61pci_config_ps()
1145 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); in rt61pci_start_queue()
1150 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1); in rt61pci_start_queue()
1151 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1); in rt61pci_start_queue()
1152 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); in rt61pci_start_queue()
1168 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0, 1); in rt61pci_kick_queue()
1173 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1, 1); in rt61pci_kick_queue()
1178 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2, 1); in rt61pci_kick_queue()
1183 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3, 1); in rt61pci_kick_queue()
1199 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, 1); in rt61pci_stop_queue()
1204 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, 1); in rt61pci_stop_queue()
1209 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, 1); in rt61pci_stop_queue()
1214 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, 1); in rt61pci_stop_queue()
1219 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 1); in rt61pci_stop_queue()
1224 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); in rt61pci_stop_queue()
1225 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); in rt61pci_stop_queue()
1226 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); in rt61pci_stop_queue()
1320 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1); in rt61pci_load_firmware()
1330 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1); in rt61pci_load_firmware()
1331 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 1); in rt61pci_load_firmware()
1337 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 0); in rt61pci_load_firmware()
1340 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 0); in rt61pci_load_firmware()
1364 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1); in rt61pci_load_firmware()
1365 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); in rt61pci_load_firmware()
1369 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); in rt61pci_load_firmware()
1370 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); in rt61pci_load_firmware()
1374 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); in rt61pci_load_firmware()
1408 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS, in rt61pci_clear_entry()
1413 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); in rt61pci_clear_entry()
1417 rt2x00_set_field32(&word, TXD_W0_VALID, 0); in rt61pci_clear_entry()
1418 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); in rt61pci_clear_entry()
1432 rt2x00_set_field32(®, TX_RING_CSR0_AC0_RING_SIZE, in rt61pci_init_queues()
1434 rt2x00_set_field32(®, TX_RING_CSR0_AC1_RING_SIZE, in rt61pci_init_queues()
1436 rt2x00_set_field32(®, TX_RING_CSR0_AC2_RING_SIZE, in rt61pci_init_queues()
1438 rt2x00_set_field32(®, TX_RING_CSR0_AC3_RING_SIZE, in rt61pci_init_queues()
1443 rt2x00_set_field32(®, TX_RING_CSR1_TXD_SIZE, in rt61pci_init_queues()
1449 rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER, in rt61pci_init_queues()
1455 rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER, in rt61pci_init_queues()
1461 rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER, in rt61pci_init_queues()
1467 rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER, in rt61pci_init_queues()
1472 rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit); in rt61pci_init_queues()
1473 rt2x00_set_field32(®, RX_RING_CSR_RXD_SIZE, in rt61pci_init_queues()
1475 rt2x00_set_field32(®, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4); in rt61pci_init_queues()
1480 rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER, in rt61pci_init_queues()
1485 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC0, 2); in rt61pci_init_queues()
1486 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC1, 2); in rt61pci_init_queues()
1487 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC2, 2); in rt61pci_init_queues()
1488 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC3, 2); in rt61pci_init_queues()
1492 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1); in rt61pci_init_queues()
1493 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1); in rt61pci_init_queues()
1494 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1); in rt61pci_init_queues()
1495 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1); in rt61pci_init_queues()
1499 rt2x00_set_field32(®, RX_CNTL_CSR_LOAD_RXD, 1); in rt61pci_init_queues()
1510 rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1); in rt61pci_init_registers()
1511 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); in rt61pci_init_registers()
1512 rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0); in rt61pci_init_registers()
1516 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */ in rt61pci_init_registers()
1517 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1); in rt61pci_init_registers()
1518 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */ in rt61pci_init_registers()
1519 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1); in rt61pci_init_registers()
1520 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */ in rt61pci_init_registers()
1521 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1); in rt61pci_init_registers()
1522 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */ in rt61pci_init_registers()
1523 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1); in rt61pci_init_registers()
1530 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13); in rt61pci_init_registers()
1531 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1); in rt61pci_init_registers()
1532 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12); in rt61pci_init_registers()
1533 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1); in rt61pci_init_registers()
1534 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11); in rt61pci_init_registers()
1535 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1); in rt61pci_init_registers()
1536 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10); in rt61pci_init_registers()
1537 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1); in rt61pci_init_registers()
1544 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7); in rt61pci_init_registers()
1545 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1); in rt61pci_init_registers()
1546 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6); in rt61pci_init_registers()
1547 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1); in rt61pci_init_registers()
1548 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5); in rt61pci_init_registers()
1549 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1); in rt61pci_init_registers()
1553 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59); in rt61pci_init_registers()
1554 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53); in rt61pci_init_registers()
1555 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49); in rt61pci_init_registers()
1556 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46); in rt61pci_init_registers()
1560 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44); in rt61pci_init_registers()
1561 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42); in rt61pci_init_registers()
1562 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42); in rt61pci_init_registers()
1563 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42); in rt61pci_init_registers()
1567 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, 0); in rt61pci_init_registers()
1568 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); in rt61pci_init_registers()
1569 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 0); in rt61pci_init_registers()
1570 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); in rt61pci_init_registers()
1571 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); in rt61pci_init_registers()
1572 rt2x00_set_field32(®, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0); in rt61pci_init_registers()
1580 rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0); in rt61pci_init_registers()
1633 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1); in rt61pci_init_registers()
1634 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); in rt61pci_init_registers()
1638 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); in rt61pci_init_registers()
1639 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); in rt61pci_init_registers()
1643 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); in rt61pci_init_registers()
1742 rt2x00_set_field32(®, INT_MASK_CSR_TXDONE, mask); in rt61pci_toggle_irq()
1743 rt2x00_set_field32(®, INT_MASK_CSR_RXDONE, mask); in rt61pci_toggle_irq()
1744 rt2x00_set_field32(®, INT_MASK_CSR_BEACON_DONE, mask); in rt61pci_toggle_irq()
1745 rt2x00_set_field32(®, INT_MASK_CSR_ENABLE_MITIGATION, mask); in rt61pci_toggle_irq()
1746 rt2x00_set_field32(®, INT_MASK_CSR_MITIGATION_PERIOD, 0xff); in rt61pci_toggle_irq()
1750 rt2x00_set_field32(®, MCU_INT_MASK_CSR_0, mask); in rt61pci_toggle_irq()
1751 rt2x00_set_field32(®, MCU_INT_MASK_CSR_1, mask); in rt61pci_toggle_irq()
1752 rt2x00_set_field32(®, MCU_INT_MASK_CSR_2, mask); in rt61pci_toggle_irq()
1753 rt2x00_set_field32(®, MCU_INT_MASK_CSR_3, mask); in rt61pci_toggle_irq()
1754 rt2x00_set_field32(®, MCU_INT_MASK_CSR_4, mask); in rt61pci_toggle_irq()
1755 rt2x00_set_field32(®, MCU_INT_MASK_CSR_5, mask); in rt61pci_toggle_irq()
1756 rt2x00_set_field32(®, MCU_INT_MASK_CSR_6, mask); in rt61pci_toggle_irq()
1757 rt2x00_set_field32(®, MCU_INT_MASK_CSR_7, mask); in rt61pci_toggle_irq()
1758 rt2x00_set_field32(®, MCU_INT_MASK_CSR_TWAKEUP, mask); in rt61pci_toggle_irq()
1790 rt2x00_set_field32(®, RX_CNTL_CSR_ENABLE_RX_DMA, 1); in rt61pci_enable_radio()
1813 rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep); in rt61pci_set_state()
1814 rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep); in rt61pci_set_state()
1883 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid); in rt61pci_write_tx_desc()
1884 rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs); in rt61pci_write_tx_desc()
1885 rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min); in rt61pci_write_tx_desc()
1886 rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max); in rt61pci_write_tx_desc()
1887 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset); in rt61pci_write_tx_desc()
1888 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, in rt61pci_write_tx_desc()
1890 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1); in rt61pci_write_tx_desc()
1894 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal); in rt61pci_write_tx_desc()
1895 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service); in rt61pci_write_tx_desc()
1896 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, in rt61pci_write_tx_desc()
1898 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, in rt61pci_write_tx_desc()
1908 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid); in rt61pci_write_tx_desc()
1909 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, entry->entry_idx); in rt61pci_write_tx_desc()
1910 rt2x00_set_field32(&word, TXD_W5_TX_POWER, in rt61pci_write_tx_desc()
1912 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1); in rt61pci_write_tx_desc()
1917 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS, in rt61pci_write_tx_desc()
1922 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, in rt61pci_write_tx_desc()
1933 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); in rt61pci_write_tx_desc()
1934 rt2x00_set_field32(&word, TXD_W0_VALID, 1); in rt61pci_write_tx_desc()
1935 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, in rt61pci_write_tx_desc()
1937 rt2x00_set_field32(&word, TXD_W0_ACK, in rt61pci_write_tx_desc()
1939 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP, in rt61pci_write_tx_desc()
1941 rt2x00_set_field32(&word, TXD_W0_OFDM, in rt61pci_write_tx_desc()
1943 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs); in rt61pci_write_tx_desc()
1944 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, in rt61pci_write_tx_desc()
1946 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, in rt61pci_write_tx_desc()
1948 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE, in rt61pci_write_tx_desc()
1950 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx); in rt61pci_write_tx_desc()
1951 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length); in rt61pci_write_tx_desc()
1952 rt2x00_set_field32(&word, TXD_W0_BURST, in rt61pci_write_tx_desc()
1954 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher); in rt61pci_write_tx_desc()
1983 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); in rt61pci_write_beacon()
2023 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); in rt61pci_write_beacon()
2044 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); in rt61pci_clear_beacon()
2265 rt2x00_set_field32(®, irq_field, 0); in rt61pci_enable_interrupt()
2283 rt2x00_set_field32(®, irq_field, 0); in rt61pci_enable_mcu_interrupt()
2857 rt2x00_set_field32(®, MAC_CSR13_DIR5, 1); in rt61pci_probe_hw()
2929 rt2x00_set_field32(®, field, queue->txop); in rt61pci_conf_tx()
2937 rt2x00_set_field32(®, field, queue->aifs); in rt61pci_conf_tx()
2941 rt2x00_set_field32(®, field, queue->cw_min); in rt61pci_conf_tx()
2945 rt2x00_set_field32(®, field, queue->cw_max); in rt61pci_conf_tx()