Lines Matching refs:rt2x00_set_field32
69 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma); in rt2800mmio_write_tx_desc()
73 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len); in rt2800mmio_write_tx_desc()
74 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1, in rt2800mmio_write_tx_desc()
76 rt2x00_set_field32(&word, TXD_W1_BURST, in rt2800mmio_write_tx_desc()
78 rt2x00_set_field32(&word, TXD_W1_SD_LEN0, txwi_size); in rt2800mmio_write_tx_desc()
79 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0); in rt2800mmio_write_tx_desc()
80 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0); in rt2800mmio_write_tx_desc()
84 rt2x00_set_field32(&word, TXD_W2_SD_PTR1, in rt2800mmio_write_tx_desc()
89 rt2x00_set_field32(&word, TXD_W3_WIV, in rt2800mmio_write_tx_desc()
91 rt2x00_set_field32(&word, TXD_W3_QSEL, 2); in rt2800mmio_write_tx_desc()
344 rt2x00_set_field32(®, irq_field, 1); in rt2800mmio_enable_interrupt()
389 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, in rt2800mmio_tbtt_tasklet()
394 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, in rt2800mmio_tbtt_tasklet()
493 rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1); in rt2800mmio_interrupt()
540 rt2x00_set_field32(®, INT_MASK_CSR_RX_DONE, 1); in rt2800mmio_toggle_irq()
541 rt2x00_set_field32(®, INT_MASK_CSR_TBTT, 1); in rt2800mmio_toggle_irq()
542 rt2x00_set_field32(®, INT_MASK_CSR_PRE_TBTT, 1); in rt2800mmio_toggle_irq()
543 rt2x00_set_field32(®, INT_MASK_CSR_TX_FIFO_STATUS, 1); in rt2800mmio_toggle_irq()
544 rt2x00_set_field32(®, INT_MASK_CSR_AUTO_WAKEUP, 1); in rt2800mmio_toggle_irq()
573 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); in rt2800mmio_start_queue()
578 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 1); in rt2800mmio_start_queue()
579 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 1); in rt2800mmio_start_queue()
580 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1); in rt2800mmio_start_queue()
584 rt2x00_set_field32(®, INT_TIMER_EN_PRE_TBTT_TIMER, 1); in rt2800mmio_start_queue()
627 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); in rt2800mmio_stop_queue()
632 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); in rt2800mmio_stop_queue()
633 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); in rt2800mmio_stop_queue()
634 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); in rt2800mmio_stop_queue()
638 rt2x00_set_field32(®, INT_TIMER_EN_PRE_TBTT_TIMER, 0); in rt2800mmio_stop_queue()
729 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma); in rt2800mmio_clear_entry()
733 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0); in rt2800mmio_clear_entry()
744 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1); in rt2800mmio_clear_entry()
824 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX0, 1); in rt2800mmio_init_registers()
825 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX1, 1); in rt2800mmio_init_registers()
826 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX2, 1); in rt2800mmio_init_registers()
827 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX3, 1); in rt2800mmio_init_registers()
828 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX4, 1); in rt2800mmio_init_registers()
829 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX5, 1); in rt2800mmio_init_registers()
830 rt2x00_set_field32(®, WPDMA_RST_IDX_DRX_IDX0, 1); in rt2800mmio_init_registers()
845 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); in rt2800mmio_init_registers()
846 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); in rt2800mmio_init_registers()
853 rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_CSR, 1); in rt2800mmio_init_registers()
854 rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_BBP, 1); in rt2800mmio_init_registers()