Lines Matching refs:FIELD32
139 #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
140 #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
141 #define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
142 #define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
143 #define E2PROM_CSR_TYPE FIELD32(0x00000030)
144 #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
145 #define E2PROM_CSR_RELOAD FIELD32(0x00000080)
151 #define AUX_OPT_BIT0 FIELD32(0x00000001)
152 #define AUX_OPT_BIT1 FIELD32(0x00000002)
153 #define AUX_OPT_BIT2 FIELD32(0x00000004)
154 #define AUX_OPT_BIT3 FIELD32(0x00000008)
155 #define AUX_OPT_BIT4 FIELD32(0x00000010)
156 #define AUX_OPT_BIT5 FIELD32(0x00000020)
157 #define AUX_OPT_BIT6 FIELD32(0x00000040)
158 #define AUX_OPT_BIT7 FIELD32(0x00000080)
159 #define AUX_OPT_BIT8 FIELD32(0x00000100)
160 #define AUX_OPT_BIT9 FIELD32(0x00000200)
161 #define AUX_OPT_BIT10 FIELD32(0x00000400)
162 #define AUX_OPT_BIT11 FIELD32(0x00000800)
163 #define AUX_OPT_BIT12 FIELD32(0x00001000)
164 #define AUX_OPT_BIT13 FIELD32(0x00002000)
165 #define AUX_OPT_BIT14 FIELD32(0x00004000)
166 #define AUX_OPT_BIT15 FIELD32(0x00008000)
167 #define LDO25_LEVEL FIELD32(0x00030000)
168 #define LDO25_LARGEA FIELD32(0x00040000)
169 #define LDO25_FRC_ON FIELD32(0x00080000)
170 #define CMB_RSV FIELD32(0x00300000)
171 #define XTAL_RDY FIELD32(0x00400000)
172 #define PLL_LD FIELD32(0x00800000)
173 #define LDO_CORE_LEVEL FIELD32(0x0F000000)
174 #define LDO_BGSEL FIELD32(0x30000000)
175 #define LDO3_EN FIELD32(0x40000000)
176 #define LDO0_EN FIELD32(0x80000000)
208 #define OSC_REF_CYCLE FIELD32(0x00001fff)
209 #define OSC_RSV FIELD32(0x0000e000)
210 #define OSC_CAL_CNT FIELD32(0x0fff0000)
211 #define OSC_CAL_ACK FIELD32(0x10000000)
212 #define OSC_CLK_32K_VLD FIELD32(0x20000000)
213 #define OSC_CAL_REQ FIELD32(0x40000000)
214 #define OSC_ROSC_EN FIELD32(0x80000000)
220 #define COEX_CFG_ANT FIELD32(0xff000000)
230 #define BT_COEX_CFG1 FIELD32(0xff000000)
231 #define BT_COEX_CFG0 FIELD32(0x00ff0000)
232 #define WL_COEX_CFG1 FIELD32(0x0000ff00)
233 #define WL_COEX_CFG0 FIELD32(0x000000ff)
239 #define PLL_RESERVED_INPUT1 FIELD32(0x000000ff)
240 #define PLL_RESERVED_INPUT2 FIELD32(0x0000ff00)
241 #define PLL_CONTROL FIELD32(0x00070000)
242 #define PLL_LPF_R1 FIELD32(0x00080000)
243 #define PLL_LPF_C1_CTRL FIELD32(0x00300000)
244 #define PLL_LPF_C2_CTRL FIELD32(0x00c00000)
245 #define PLL_CP_CURRENT_CTRL FIELD32(0x03000000)
246 #define PLL_PFD_DELAY_CTRL FIELD32(0x0c000000)
247 #define PLL_LOCK_CTRL FIELD32(0x70000000)
248 #define PLL_VBGBK_EN FIELD32(0x80000000)
256 #define WLAN_EN FIELD32(0x00000001)
257 #define WLAN_CLK_EN FIELD32(0x00000002)
258 #define WLAN_RSV1 FIELD32(0x00000004)
259 #define WLAN_RESET FIELD32(0x00000008)
260 #define PCIE_APP0_CLK_REQ FIELD32(0x00000010)
261 #define FRC_WL_ANT_SET FIELD32(0x00000020)
262 #define INV_TR_SW0 FIELD32(0x00000040)
263 #define WLAN_GPIO_IN_BIT0 FIELD32(0x00000100)
264 #define WLAN_GPIO_IN_BIT1 FIELD32(0x00000200)
265 #define WLAN_GPIO_IN_BIT2 FIELD32(0x00000400)
266 #define WLAN_GPIO_IN_BIT3 FIELD32(0x00000800)
267 #define WLAN_GPIO_IN_BIT4 FIELD32(0x00001000)
268 #define WLAN_GPIO_IN_BIT5 FIELD32(0x00002000)
269 #define WLAN_GPIO_IN_BIT6 FIELD32(0x00004000)
270 #define WLAN_GPIO_IN_BIT7 FIELD32(0x00008000)
271 #define WLAN_GPIO_IN_BIT_ALL FIELD32(0x0000ff00)
272 #define WLAN_GPIO_OUT_BIT0 FIELD32(0x00010000)
273 #define WLAN_GPIO_OUT_BIT1 FIELD32(0x00020000)
274 #define WLAN_GPIO_OUT_BIT2 FIELD32(0x00040000)
275 #define WLAN_GPIO_OUT_BIT3 FIELD32(0x00050000)
276 #define WLAN_GPIO_OUT_BIT4 FIELD32(0x00100000)
277 #define WLAN_GPIO_OUT_BIT5 FIELD32(0x00200000)
278 #define WLAN_GPIO_OUT_BIT6 FIELD32(0x00400000)
279 #define WLAN_GPIO_OUT_BIT7 FIELD32(0x00800000)
280 #define WLAN_GPIO_OUT_BIT_ALL FIELD32(0x00ff0000)
281 #define WLAN_GPIO_OUT_OE_BIT0 FIELD32(0x01000000)
282 #define WLAN_GPIO_OUT_OE_BIT1 FIELD32(0x02000000)
283 #define WLAN_GPIO_OUT_OE_BIT2 FIELD32(0x04000000)
284 #define WLAN_GPIO_OUT_OE_BIT3 FIELD32(0x08000000)
285 #define WLAN_GPIO_OUT_OE_BIT4 FIELD32(0x10000000)
286 #define WLAN_GPIO_OUT_OE_BIT5 FIELD32(0x20000000)
287 #define WLAN_GPIO_OUT_OE_BIT6 FIELD32(0x40000000)
288 #define WLAN_GPIO_OUT_OE_BIT7 FIELD32(0x80000000)
289 #define WLAN_GPIO_OUT_OE_BIT_ALL FIELD32(0xff000000)
295 #define AUX_CTRL_WAKE_PCIE_EN FIELD32(0x00000002)
296 #define AUX_CTRL_FORCE_PCIE_CLK FIELD32(0x00000400)
302 #define OPT_14_CSR_BIT0 FIELD32(0x00000001)
310 #define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
311 #define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
312 #define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
313 #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
314 #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
315 #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
316 #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
317 #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
318 #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
319 #define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
320 #define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
321 #define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
322 #define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
323 #define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
324 #define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
325 #define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
326 #define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
327 #define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
333 #define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
334 #define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
335 #define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
336 #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
337 #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
338 #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
339 #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
340 #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
341 #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
342 #define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
343 #define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
344 #define INT_MASK_CSR_TBTT FIELD32(0x00000800)
345 #define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
346 #define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
347 #define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
348 #define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
349 #define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
350 #define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
356 #define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
357 #define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
358 #define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
359 #define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
360 #define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
361 #define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
362 #define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
363 #define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
364 #define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
370 #define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
371 #define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
372 #define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
373 #define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
374 #define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
375 #define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
376 #define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
382 #define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
383 #define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
384 #define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
385 #define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
386 #define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
387 #define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
397 #define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
398 #define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
399 #define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
400 #define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
410 #define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
411 #define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
412 #define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
413 #define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
423 #define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
424 #define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
425 #define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
426 #define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
434 #define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
435 #define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
443 #define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
444 #define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
452 #define GPIO_CTRL_VAL0 FIELD32(0x00000001)
453 #define GPIO_CTRL_VAL1 FIELD32(0x00000002)
454 #define GPIO_CTRL_VAL2 FIELD32(0x00000004)
455 #define GPIO_CTRL_VAL3 FIELD32(0x00000008)
456 #define GPIO_CTRL_VAL4 FIELD32(0x00000010)
457 #define GPIO_CTRL_VAL5 FIELD32(0x00000020)
458 #define GPIO_CTRL_VAL6 FIELD32(0x00000040)
459 #define GPIO_CTRL_VAL7 FIELD32(0x00000080)
460 #define GPIO_CTRL_DIR0 FIELD32(0x00000100)
461 #define GPIO_CTRL_DIR1 FIELD32(0x00000200)
462 #define GPIO_CTRL_DIR2 FIELD32(0x00000400)
463 #define GPIO_CTRL_DIR3 FIELD32(0x00000800)
464 #define GPIO_CTRL_DIR4 FIELD32(0x00001000)
465 #define GPIO_CTRL_DIR5 FIELD32(0x00002000)
466 #define GPIO_CTRL_DIR6 FIELD32(0x00004000)
467 #define GPIO_CTRL_DIR7 FIELD32(0x00008000)
468 #define GPIO_CTRL_VAL8 FIELD32(0x00010000)
469 #define GPIO_CTRL_VAL9 FIELD32(0x00020000)
470 #define GPIO_CTRL_VAL10 FIELD32(0x00040000)
471 #define GPIO_CTRL_DIR8 FIELD32(0x01000000)
472 #define GPIO_CTRL_DIR9 FIELD32(0x02000000)
473 #define GPIO_CTRL_DIR10 FIELD32(0x04000000)
551 #define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
552 #define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00)
553 #define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000)
554 #define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000)
555 #define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000)
556 #define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000)
557 #define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000)
558 #define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000)
559 #define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000)
560 #define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000)
561 #define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000)
570 #define US_CYC_CNT_BT_MODE_EN FIELD32(0x00000100)
571 #define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff)
578 #define PBF_SYS_CTRL_READY FIELD32(0x00000080)
579 #define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
585 #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
601 #define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
602 #define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
603 #define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
604 #define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
610 #define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
611 #define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
612 #define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
613 #define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
623 #define TXRXQ_PCNT_TX0Q FIELD32(0x000000ff)
624 #define TXRXQ_PCNT_TX1Q FIELD32(0x0000ff00)
625 #define TXRXQ_PCNT_TX2Q FIELD32(0x00ff0000)
626 #define TXRXQ_PCNT_RX0Q FIELD32(0xff000000)
638 #define RF_CSR_CFG_DATA FIELD32(0x000000ff)
639 #define RF_CSR_CFG_REGNUM FIELD32(0x00003f00)
640 #define RF_CSR_CFG_WRITE FIELD32(0x00010000)
641 #define RF_CSR_CFG_BUSY FIELD32(0x00020000)
646 #define RF_CSR_CFG_DATA_MT7620 FIELD32(0x0000ff00)
647 #define RF_CSR_CFG_REGNUM_MT7620 FIELD32(0x03ff0000)
648 #define RF_CSR_CFG_WRITE_MT7620 FIELD32(0x00000010)
649 #define RF_CSR_CFG_BUSY_MT7620 FIELD32(0x00000001)
665 #define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000)
666 #define EFUSE_CTRL_MODE FIELD32(0x000000c0)
667 #define EFUSE_CTRL_KICK FIELD32(0x40000000)
668 #define EFUSE_CTRL_PRESENT FIELD32(0x80000000)
694 #define LDO_CFG0_DELAY3 FIELD32(0x000000ff)
695 #define LDO_CFG0_DELAY2 FIELD32(0x0000ff00)
696 #define LDO_CFG0_DELAY1 FIELD32(0x00ff0000)
697 #define LDO_CFG0_BGSEL FIELD32(0x03000000)
698 #define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000)
699 #define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000)
700 #define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000)
706 #define GPIO_SWITCH_0 FIELD32(0x00000001)
707 #define GPIO_SWITCH_1 FIELD32(0x00000002)
708 #define GPIO_SWITCH_2 FIELD32(0x00000004)
709 #define GPIO_SWITCH_3 FIELD32(0x00000008)
710 #define GPIO_SWITCH_4 FIELD32(0x00000010)
711 #define GPIO_SWITCH_5 FIELD32(0x00000020)
712 #define GPIO_SWITCH_6 FIELD32(0x00000040)
713 #define GPIO_SWITCH_7 FIELD32(0x00000080)
719 #define MAC_DEBUG_INDEX_XTAL FIELD32(0x80000000)
732 #define MAC_CSR0_REVISION FIELD32(0x0000ffff)
733 #define MAC_CSR0_CHIPSET FIELD32(0xffff0000)
739 #define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
740 #define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
741 #define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
742 #define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
743 #define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
744 #define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
745 #define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
746 #define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
752 #define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
753 #define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
754 #define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
755 #define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
766 #define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
767 #define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
768 #define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
774 #define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
775 #define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
776 #define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
777 #define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
791 #define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
792 #define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
793 #define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
794 #define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
803 #define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
804 #define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
805 #define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
806 #define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
818 #define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
819 #define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
820 #define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
821 #define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
822 #define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
823 #define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
834 #define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
835 #define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
836 #define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
837 #define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
838 #define RF_CSR_CFG0_SEL FIELD32(0x40000000)
839 #define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
849 #define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
850 #define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
857 #define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
874 #define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
875 #define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
876 #define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
877 #define LED_CFG_R_LED_MODE FIELD32(0x03000000)
878 #define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
879 #define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
880 #define LED_CFG_LED_POLAR FIELD32(0x40000000)
891 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE FIELD32(0x00000020)
892 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE FIELD32(0x0000001f)
905 #define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
906 #define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
907 #define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
908 #define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
909 #define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
915 #define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
916 #define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
922 #define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
923 #define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
924 #define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
925 #define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
936 #define CH_TIME_CFG_EIFS_BUSY FIELD32(0x00000010)
937 #define CH_TIME_CFG_NAV_BUSY FIELD32(0x00000008)
938 #define CH_TIME_CFG_RX_BUSY FIELD32(0x00000004)
939 #define CH_TIME_CFG_TX_BUSY FIELD32(0x00000002)
940 #define CH_TIME_CFG_TMR_EN FIELD32(0x00000001)
955 #define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
956 #define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
957 #define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
958 #define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
959 #define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
960 #define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
968 #define TBTT_SYNC_CFG_TBTT_ADJUST FIELD32(0x000000ff)
969 #define TBTT_SYNC_CFG_BCN_EXP_WIN FIELD32(0x0000ff00)
970 #define TBTT_SYNC_CFG_BCN_AIFSN FIELD32(0x000f0000)
971 #define TBTT_SYNC_CFG_BCN_CWMIN FIELD32(0x00f00000)
977 #define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
983 #define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
996 #define INT_TIMER_CFG_PRE_TBTT_TIMER FIELD32(0x0000ffff)
997 #define INT_TIMER_CFG_GP_TIMER FIELD32(0xffff0000)
1003 #define INT_TIMER_EN_PRE_TBTT_TIMER FIELD32(0x00000001)
1004 #define INT_TIMER_EN_GP_TIMER FIELD32(0x00000002)
1027 #define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
1040 #define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
1041 #define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
1042 #define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
1048 #define MIMO_PS_CFG_MMPS_BB_EN FIELD32(0x00000001)
1049 #define MIMO_PS_CFG_MMPS_RX_ANT_NUM FIELD32(0x00000006)
1050 #define MIMO_PS_CFG_MMPS_RF_EN FIELD32(0x00000008)
1051 #define MIMO_PS_CFG_RX_STBY_POL FIELD32(0x00000010)
1052 #define MIMO_PS_CFG_RX_RX_STBY0 FIELD32(0x00000020)
1058 #define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
1059 #define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
1060 #define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
1061 #define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
1067 #define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
1068 #define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
1069 #define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
1070 #define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
1076 #define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
1077 #define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
1078 #define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
1079 #define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
1085 #define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
1086 #define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
1087 #define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
1088 #define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
1098 #define TX_PWR_CFG_RATE0 FIELD32(0x0000000f)
1099 #define TX_PWR_CFG_RATE1 FIELD32(0x000000f0)
1100 #define TX_PWR_CFG_RATE2 FIELD32(0x00000f00)
1101 #define TX_PWR_CFG_RATE3 FIELD32(0x0000f000)
1102 #define TX_PWR_CFG_RATE4 FIELD32(0x000f0000)
1103 #define TX_PWR_CFG_RATE5 FIELD32(0x00f00000)
1104 #define TX_PWR_CFG_RATE6 FIELD32(0x0f000000)
1105 #define TX_PWR_CFG_RATE7 FIELD32(0xf0000000)
1111 #define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
1112 #define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
1113 #define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
1114 #define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
1115 #define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
1116 #define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
1117 #define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
1118 #define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
1120 #define TX_PWR_CFG_0_CCK1_CH0 FIELD32(0x0000000f)
1121 #define TX_PWR_CFG_0_CCK1_CH1 FIELD32(0x000000f0)
1122 #define TX_PWR_CFG_0_CCK5_CH0 FIELD32(0x00000f00)
1123 #define TX_PWR_CFG_0_CCK5_CH1 FIELD32(0x0000f000)
1124 #define TX_PWR_CFG_0_OFDM6_CH0 FIELD32(0x000f0000)
1125 #define TX_PWR_CFG_0_OFDM6_CH1 FIELD32(0x00f00000)
1126 #define TX_PWR_CFG_0_OFDM12_CH0 FIELD32(0x0f000000)
1127 #define TX_PWR_CFG_0_OFDM12_CH1 FIELD32(0xf0000000)
1129 #define TX_PWR_CFG_0B_1MBS_2MBS FIELD32(0x000000ff)
1130 #define TX_PWR_CFG_0B_5MBS_11MBS FIELD32(0x0000ff00)
1131 #define TX_PWR_CFG_0B_6MBS_9MBS FIELD32(0x00ff0000)
1132 #define TX_PWR_CFG_0B_12MBS_18MBS FIELD32(0xff000000)
1139 #define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
1140 #define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
1141 #define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
1142 #define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
1143 #define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
1144 #define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
1145 #define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
1146 #define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
1148 #define TX_PWR_CFG_1_OFDM24_CH0 FIELD32(0x0000000f)
1149 #define TX_PWR_CFG_1_OFDM24_CH1 FIELD32(0x000000f0)
1150 #define TX_PWR_CFG_1_OFDM48_CH0 FIELD32(0x00000f00)
1151 #define TX_PWR_CFG_1_OFDM48_CH1 FIELD32(0x0000f000)
1152 #define TX_PWR_CFG_1_MCS0_CH0 FIELD32(0x000f0000)
1153 #define TX_PWR_CFG_1_MCS0_CH1 FIELD32(0x00f00000)
1154 #define TX_PWR_CFG_1_MCS2_CH0 FIELD32(0x0f000000)
1155 #define TX_PWR_CFG_1_MCS2_CH1 FIELD32(0xf0000000)
1157 #define TX_PWR_CFG_1B_24MBS_36MBS FIELD32(0x000000ff)
1158 #define TX_PWR_CFG_1B_48MBS FIELD32(0x0000ff00)
1159 #define TX_PWR_CFG_1B_MCS0_MCS1 FIELD32(0x00ff0000)
1160 #define TX_PWR_CFG_1B_MCS2_MCS3 FIELD32(0xff000000)
1166 #define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
1167 #define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
1168 #define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
1169 #define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
1170 #define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
1171 #define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
1172 #define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
1173 #define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
1175 #define TX_PWR_CFG_2_MCS4_CH0 FIELD32(0x0000000f)
1176 #define TX_PWR_CFG_2_MCS4_CH1 FIELD32(0x000000f0)
1177 #define TX_PWR_CFG_2_MCS6_CH0 FIELD32(0x00000f00)
1178 #define TX_PWR_CFG_2_MCS6_CH1 FIELD32(0x0000f000)
1179 #define TX_PWR_CFG_2_MCS8_CH0 FIELD32(0x000f0000)
1180 #define TX_PWR_CFG_2_MCS8_CH1 FIELD32(0x00f00000)
1181 #define TX_PWR_CFG_2_MCS10_CH0 FIELD32(0x0f000000)
1182 #define TX_PWR_CFG_2_MCS10_CH1 FIELD32(0xf0000000)
1184 #define TX_PWR_CFG_2B_MCS4_MCS5 FIELD32(0x000000ff)
1185 #define TX_PWR_CFG_2B_MCS6_MCS7 FIELD32(0x0000ff00)
1186 #define TX_PWR_CFG_2B_MCS8_MCS9 FIELD32(0x00ff0000)
1187 #define TX_PWR_CFG_2B_MCS10_MCS11 FIELD32(0xff000000)
1193 #define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
1194 #define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
1195 #define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
1196 #define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
1197 #define TX_PWR_CFG_3_UNKNOWN1 FIELD32(0x000f0000)
1198 #define TX_PWR_CFG_3_UNKNOWN2 FIELD32(0x00f00000)
1199 #define TX_PWR_CFG_3_UNKNOWN3 FIELD32(0x0f000000)
1200 #define TX_PWR_CFG_3_UNKNOWN4 FIELD32(0xf0000000)
1202 #define TX_PWR_CFG_3_MCS12_CH0 FIELD32(0x0000000f)
1203 #define TX_PWR_CFG_3_MCS12_CH1 FIELD32(0x000000f0)
1204 #define TX_PWR_CFG_3_MCS14_CH0 FIELD32(0x00000f00)
1205 #define TX_PWR_CFG_3_MCS14_CH1 FIELD32(0x0000f000)
1206 #define TX_PWR_CFG_3_STBC0_CH0 FIELD32(0x000f0000)
1207 #define TX_PWR_CFG_3_STBC0_CH1 FIELD32(0x00f00000)
1208 #define TX_PWR_CFG_3_STBC2_CH0 FIELD32(0x0f000000)
1209 #define TX_PWR_CFG_3_STBC2_CH1 FIELD32(0xf0000000)
1211 #define TX_PWR_CFG_3B_MCS12_MCS13 FIELD32(0x000000ff)
1212 #define TX_PWR_CFG_3B_MCS14 FIELD32(0x0000ff00)
1213 #define TX_PWR_CFG_3B_STBC_MCS0_MCS1 FIELD32(0x00ff0000)
1214 #define TX_PWR_CFG_3B_STBC_MCS2_MSC3 FIELD32(0xff000000)
1220 #define TX_PWR_CFG_4_UNKNOWN5 FIELD32(0x0000000f)
1221 #define TX_PWR_CFG_4_UNKNOWN6 FIELD32(0x000000f0)
1222 #define TX_PWR_CFG_4_UNKNOWN7 FIELD32(0x00000f00)
1223 #define TX_PWR_CFG_4_UNKNOWN8 FIELD32(0x0000f000)
1225 #define TX_PWR_CFG_4_STBC4_CH0 FIELD32(0x0000000f)
1226 #define TX_PWR_CFG_4_STBC4_CH1 FIELD32(0x000000f0)
1227 #define TX_PWR_CFG_4_STBC6_CH0 FIELD32(0x00000f00)
1228 #define TX_PWR_CFG_4_STBC6_CH1 FIELD32(0x0000f000)
1230 #define TX_PWR_CFG_4B_STBC_MCS4_MCS5 FIELD32(0x000000ff)
1231 #define TX_PWR_CFG_4B_STBC_MCS6 FIELD32(0x0000ff00)
1238 #define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
1239 #define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
1240 #define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
1241 #define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
1242 #define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
1243 #define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
1244 #define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
1245 #define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
1246 #define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
1247 #define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
1248 #define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
1249 #define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
1250 #define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
1251 #define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
1252 #define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
1253 #define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
1254 #define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
1255 #define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
1256 #define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
1257 #define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
1258 #define TX_PIN_CFG_RFRX_EN FIELD32(0x00100000)
1259 #define TX_PIN_CFG_RFRX_POL FIELD32(0x00200000)
1260 #define TX_PIN_CFG_PA_PE_A2_EN FIELD32(0x01000000)
1261 #define TX_PIN_CFG_PA_PE_G2_EN FIELD32(0x02000000)
1262 #define TX_PIN_CFG_PA_PE_A2_POL FIELD32(0x04000000)
1263 #define TX_PIN_CFG_PA_PE_G2_POL FIELD32(0x08000000)
1264 #define TX_PIN_CFG_LNA_PE_A2_EN FIELD32(0x10000000)
1265 #define TX_PIN_CFG_LNA_PE_G2_EN FIELD32(0x20000000)
1266 #define TX_PIN_CFG_LNA_PE_A2_POL FIELD32(0x40000000)
1267 #define TX_PIN_CFG_LNA_PE_G2_POL FIELD32(0x80000000)
1273 #define TX_BAND_CFG_HT40_MINUS FIELD32(0x00000001)
1274 #define TX_BAND_CFG_A FIELD32(0x00000002)
1275 #define TX_BAND_CFG_BG FIELD32(0x00000004)
1314 #define TXOP_CTRL_CFG_TIMEOUT_TRUN_EN FIELD32(0x00000001)
1315 #define TXOP_CTRL_CFG_AC_TRUN_EN FIELD32(0x00000002)
1316 #define TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN FIELD32(0x00000004)
1317 #define TXOP_CTRL_CFG_USER_MODE_TRUN_EN FIELD32(0x00000008)
1318 #define TXOP_CTRL_CFG_MIMO_PS_TRUN_EN FIELD32(0x00000010)
1319 #define TXOP_CTRL_CFG_RESERVED_TRUN_EN FIELD32(0x00000020)
1320 #define TXOP_CTRL_CFG_LSIG_TXOP_EN FIELD32(0x00000040)
1321 #define TXOP_CTRL_CFG_EXT_CCA_EN FIELD32(0x00000080)
1322 #define TXOP_CTRL_CFG_EXT_CCA_DLY FIELD32(0x0000ff00)
1323 #define TXOP_CTRL_CFG_EXT_CWMIN FIELD32(0x000f0000)
1331 #define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
1332 #define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
1333 #define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
1344 #define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
1345 #define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
1346 #define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
1360 #define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
1361 #define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
1362 #define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
1363 #define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
1364 #define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
1365 #define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
1380 #define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
1381 #define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
1382 #define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
1383 #define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
1384 #define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
1385 #define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
1386 #define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
1387 #define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
1393 #define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
1394 #define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
1395 #define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
1396 #define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
1397 #define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
1398 #define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
1399 #define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
1400 #define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
1406 #define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
1407 #define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
1408 #define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
1409 #define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
1410 #define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
1411 #define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
1412 #define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
1413 #define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
1419 #define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
1420 #define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
1421 #define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
1422 #define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
1423 #define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
1424 #define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
1425 #define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
1426 #define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
1432 #define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
1433 #define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
1434 #define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
1435 #define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
1453 #define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1454 #define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1455 #define CCK_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1456 #define CCK_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1457 #define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1458 #define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1459 #define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1460 #define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1461 #define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1462 #define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1463 #define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1469 #define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1470 #define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1471 #define OFDM_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1472 #define OFDM_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1473 #define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1474 #define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1475 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1476 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1477 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1478 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1479 #define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1485 #define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1486 #define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1487 #define MM20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1488 #define MM20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1489 #define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1490 #define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1491 #define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1492 #define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1493 #define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1494 #define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1495 #define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1501 #define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1502 #define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1503 #define MM40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1504 #define MM40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1505 #define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1506 #define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1507 #define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1508 #define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1509 #define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1510 #define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1511 #define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1517 #define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1518 #define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1519 #define GF20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1520 #define GF20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1521 #define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1522 #define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1523 #define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1524 #define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1525 #define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1526 #define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1527 #define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1533 #define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1534 #define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1535 #define GF40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1536 #define GF40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1537 #define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1538 #define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1539 #define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1540 #define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1541 #define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1542 #define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1543 #define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1557 #define TX_PWR_CFG_5_MCS16_CH0 FIELD32(0x0000000f)
1558 #define TX_PWR_CFG_5_MCS16_CH1 FIELD32(0x000000f0)
1559 #define TX_PWR_CFG_5_MCS16_CH2 FIELD32(0x00000f00)
1560 #define TX_PWR_CFG_5_MCS18_CH0 FIELD32(0x000f0000)
1561 #define TX_PWR_CFG_5_MCS18_CH1 FIELD32(0x00f00000)
1562 #define TX_PWR_CFG_5_MCS18_CH2 FIELD32(0x0f000000)
1566 #define TX_PWR_CFG_6_MCS20_CH0 FIELD32(0x0000000f)
1567 #define TX_PWR_CFG_6_MCS20_CH1 FIELD32(0x000000f0)
1568 #define TX_PWR_CFG_6_MCS20_CH2 FIELD32(0x00000f00)
1569 #define TX_PWR_CFG_6_MCS22_CH0 FIELD32(0x000f0000)
1570 #define TX_PWR_CFG_6_MCS22_CH1 FIELD32(0x00f00000)
1571 #define TX_PWR_CFG_6_MCS22_CH2 FIELD32(0x0f000000)
1575 #define TX_PWR_CFG_0_EXT_CCK1_CH2 FIELD32(0x0000000f)
1576 #define TX_PWR_CFG_0_EXT_CCK5_CH2 FIELD32(0x00000f00)
1577 #define TX_PWR_CFG_0_EXT_OFDM6_CH2 FIELD32(0x000f0000)
1578 #define TX_PWR_CFG_0_EXT_OFDM12_CH2 FIELD32(0x0f000000)
1582 #define TX_PWR_CFG_1_EXT_OFDM24_CH2 FIELD32(0x0000000f)
1583 #define TX_PWR_CFG_1_EXT_OFDM48_CH2 FIELD32(0x00000f00)
1584 #define TX_PWR_CFG_1_EXT_MCS0_CH2 FIELD32(0x000f0000)
1585 #define TX_PWR_CFG_1_EXT_MCS2_CH2 FIELD32(0x0f000000)
1589 #define TX_PWR_CFG_2_EXT_MCS4_CH2 FIELD32(0x0000000f)
1590 #define TX_PWR_CFG_2_EXT_MCS6_CH2 FIELD32(0x00000f00)
1591 #define TX_PWR_CFG_2_EXT_MCS8_CH2 FIELD32(0x000f0000)
1592 #define TX_PWR_CFG_2_EXT_MCS10_CH2 FIELD32(0x0f000000)
1596 #define TX_PWR_CFG_3_EXT_MCS12_CH2 FIELD32(0x0000000f)
1597 #define TX_PWR_CFG_3_EXT_MCS14_CH2 FIELD32(0x00000f00)
1598 #define TX_PWR_CFG_3_EXT_STBC0_CH2 FIELD32(0x000f0000)
1599 #define TX_PWR_CFG_3_EXT_STBC2_CH2 FIELD32(0x0f000000)
1603 #define TX_PWR_CFG_4_EXT_STBC4_CH2 FIELD32(0x0000000f)
1604 #define TX_PWR_CFG_4_EXT_STBC6_CH2 FIELD32(0x00000f00)
1610 #define TX0_RF_GAIN_CORRECT_GAIN_CORR_0 FIELD32(0x0000003f)
1611 #define TX0_RF_GAIN_CORRECT_GAIN_CORR_1 FIELD32(0x00003f00)
1612 #define TX0_RF_GAIN_CORRECT_GAIN_CORR_2 FIELD32(0x003f0000)
1613 #define TX0_RF_GAIN_CORRECT_GAIN_CORR_3 FIELD32(0x3f000000)
1616 #define TX1_RF_GAIN_CORRECT_GAIN_CORR_0 FIELD32(0x0000003f)
1617 #define TX1_RF_GAIN_CORRECT_GAIN_CORR_1 FIELD32(0x00003f00)
1618 #define TX1_RF_GAIN_CORRECT_GAIN_CORR_2 FIELD32(0x003f0000)
1619 #define TX1_RF_GAIN_CORRECT_GAIN_CORR_3 FIELD32(0x3f000000)
1626 #define TX0_RF_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000007f)
1627 #define TX0_RF_GAIN_ATTEN_LEVEL_1 FIELD32(0x00007f00)
1628 #define TX0_RF_GAIN_ATTEN_LEVEL_2 FIELD32(0x007f0000)
1629 #define TX0_RF_GAIN_ATTEN_LEVEL_3 FIELD32(0x7f000000)
1631 #define TX1_RF_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000007f)
1632 #define TX1_RF_GAIN_ATTEN_LEVEL_1 FIELD32(0x00007f00)
1633 #define TX1_RF_GAIN_ATTEN_LEVEL_2 FIELD32(0x007f0000)
1634 #define TX1_RF_GAIN_ATTEN_LEVEL_3 FIELD32(0x7f000000)
1642 #define TX_ALC_CFG_0_CH_INIT_0 FIELD32(0x0000003f)
1643 #define TX_ALC_CFG_0_CH_INIT_1 FIELD32(0x00003f00)
1644 #define TX_ALC_CFG_0_LIMIT_0 FIELD32(0x003f0000)
1645 #define TX_ALC_CFG_0_LIMIT_1 FIELD32(0x3f000000)
1663 #define TX_ALC_CFG_1_TX_TEMP_COMP FIELD32(0x0000003f)
1664 #define TX_ALC_CFG_1_TX0_GAIN_FINE FIELD32(0x00000f00)
1665 #define TX_ALC_CFG_1_TX1_GAIN_FINE FIELD32(0x0000f000)
1666 #define TX_ALC_CFG_1_RF_TOS_DLY FIELD32(0x00070000)
1667 #define TX_ALC_CFG_1_TX0_RF_GAIN_ATTEN FIELD32(0x00300000)
1668 #define TX_ALC_CFG_1_TX1_RF_GAIN_ATTEN FIELD32(0x00c00000)
1669 #define TX_ALC_CFG_1_RF_TOS_TIMEOUT FIELD32(0x3f000000)
1670 #define TX_ALC_CFG_1_RF_TOS_ENABLE FIELD32(0x40000000)
1671 #define TX_ALC_CFG_1_ROS_BUSY_EN FIELD32(0x80000000)
1678 #define TX0_BB_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000001f)
1679 #define TX0_BB_GAIN_ATTEN_LEVEL_1 FIELD32(0x00001f00)
1680 #define TX0_BB_GAIN_ATTEN_LEVEL_2 FIELD32(0x001f0000)
1681 #define TX0_BB_GAIN_ATTEN_LEVEL_3 FIELD32(0x1f000000)
1683 #define TX1_BB_GAIN_ATTEN_LEVEL_0 FIELD32(0x0000001f)
1684 #define TX1_BB_GAIN_ATTEN_LEVEL_1 FIELD32(0x00001f00)
1685 #define TX1_BB_GAIN_ATTEN_LEVEL_2 FIELD32(0x001f0000)
1686 #define TX1_BB_GAIN_ATTEN_LEVEL_3 FIELD32(0x1f000000)
1690 #define TX_ALC_VGA3_TX0_ALC_VGA3 FIELD32(0x0000001f)
1691 #define TX_ALC_VGA3_TX1_ALC_VGA3 FIELD32(0x00001f00)
1692 #define TX_ALC_VGA3_TX0_ALC_VGA2 FIELD32(0x001f0000)
1693 #define TX_ALC_VGA3_TX1_ALC_VGA2 FIELD32(0x1f000000)
1697 #define TX_PWR_CFG_7_OFDM54_CH0 FIELD32(0x0000000f)
1698 #define TX_PWR_CFG_7_OFDM54_CH1 FIELD32(0x000000f0)
1699 #define TX_PWR_CFG_7_OFDM54_CH2 FIELD32(0x00000f00)
1700 #define TX_PWR_CFG_7_MCS7_CH0 FIELD32(0x000f0000)
1701 #define TX_PWR_CFG_7_MCS7_CH1 FIELD32(0x00f00000)
1702 #define TX_PWR_CFG_7_MCS7_CH2 FIELD32(0x0f000000)
1704 #define TX_PWR_CFG_7B_54MBS FIELD32(0x000000ff)
1705 #define TX_PWR_CFG_7B_MCS7 FIELD32(0x00ff0000)
1710 #define TX_PWR_CFG_8_MCS15_CH0 FIELD32(0x0000000f)
1711 #define TX_PWR_CFG_8_MCS15_CH1 FIELD32(0x000000f0)
1712 #define TX_PWR_CFG_8_MCS15_CH2 FIELD32(0x00000f00)
1713 #define TX_PWR_CFG_8_MCS23_CH0 FIELD32(0x000f0000)
1714 #define TX_PWR_CFG_8_MCS23_CH1 FIELD32(0x00f00000)
1715 #define TX_PWR_CFG_8_MCS23_CH2 FIELD32(0x0f000000)
1717 #define TX_PWR_CFG_8B_MCS15 FIELD32(0x000000ff)
1722 #define TX_PWR_CFG_9_STBC7_CH0 FIELD32(0x0000000f)
1723 #define TX_PWR_CFG_9_STBC7_CH1 FIELD32(0x000000f0)
1724 #define TX_PWR_CFG_9_STBC7_CH2 FIELD32(0x00000f00)
1726 #define TX_PWR_CFG_9B_STBC_MCS7 FIELD32(0x000000ff)
1732 #define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
1733 #define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
1734 #define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
1735 #define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
1736 #define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
1737 #define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
1738 #define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
1739 #define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
1740 #define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
1741 #define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
1742 #define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
1743 #define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
1744 #define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
1745 #define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
1746 #define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
1747 #define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
1748 #define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
1761 #define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
1762 #define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
1763 #define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
1764 #define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
1765 #define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
1766 #define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
1767 #define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
1844 #define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
1845 #define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
1851 #define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
1852 #define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
1858 #define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
1859 #define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
1865 #define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
1866 #define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
1872 #define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
1873 #define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
1879 #define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
1880 #define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1907 #define TX_STA_FIFO_VALID FIELD32(0x00000001)
1908 #define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1909 #define TX_STA_FIFO_PID_QUEUE FIELD32(0x00000006)
1910 #define TX_STA_FIFO_PID_ENTRY FIELD32(0x00000018)
1911 #define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1912 #define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1913 #define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
1914 #define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
1915 #define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
1916 #define TX_STA_FIFO_MCS FIELD32(0x007f0000)
1917 #define TX_STA_FIFO_BW FIELD32(0x00800000)
1918 #define TX_STA_FIFO_SGI FIELD32(0x01000000)
1919 #define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000)
1925 #define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
1926 #define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
1932 #define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
1933 #define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
1939 #define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
1940 #define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
1946 #define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
1947 #define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
1953 #define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
1954 #define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
1960 #define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
1961 #define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
1967 #define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
1968 #define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
1974 #define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
1975 #define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
1981 #define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
1982 #define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
1990 #define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
1991 #define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
2058 #define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
2059 #define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
2060 #define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
2061 #define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
2062 #define MAC_WCID_ATTRIBUTE_CIPHER_EXT FIELD32(0x00000400)
2063 #define MAC_WCID_ATTRIBUTE_BSS_IDX_EXT FIELD32(0x00000800)
2064 #define MAC_WCID_ATTRIBUTE_WAPI_MCBC FIELD32(0x00008000)
2065 #define MAC_WCID_ATTRIBUTE_WAPI_KEY_IDX FIELD32(0xff000000)
2070 #define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
2071 #define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
2072 #define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
2073 #define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
2074 #define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
2075 #define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
2076 #define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
2077 #define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
2088 #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
2089 #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
2090 #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
2091 #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
2099 #define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
2100 #define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
2101 #define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
2102 #define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
2559 #define RF2_ANTENNA_RX2 FIELD32(0x00000040)
2560 #define RF2_ANTENNA_TX1 FIELD32(0x00004000)
2561 #define RF2_ANTENNA_RX1 FIELD32(0x00020000)
2566 #define RF3_TXPOWER_G FIELD32(0x00003e00)
2567 #define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
2568 #define RF3_TXPOWER_A FIELD32(0x00003c00)
2573 #define RF4_TXPOWER_G FIELD32(0x000007c0)
2574 #define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
2575 #define RF4_TXPOWER_A FIELD32(0x00000780)
2576 #define RF4_FREQ_OFFSET FIELD32(0x001f8000)
2577 #define RF4_HT40 FIELD32(0x00200000)
3053 #define TXWI_W0_FRAG FIELD32(0x00000001)
3054 #define TXWI_W0_MIMO_PS FIELD32(0x00000002)
3055 #define TXWI_W0_CF_ACK FIELD32(0x00000004)
3056 #define TXWI_W0_TS FIELD32(0x00000008)
3057 #define TXWI_W0_AMPDU FIELD32(0x00000010)
3058 #define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
3059 #define TXWI_W0_TX_OP FIELD32(0x00000300)
3060 #define TXWI_W0_MCS FIELD32(0x007f0000)
3061 #define TXWI_W0_BW FIELD32(0x00800000)
3062 #define TXWI_W0_SHORT_GI FIELD32(0x01000000)
3063 #define TXWI_W0_STBC FIELD32(0x06000000)
3064 #define TXWI_W0_IFS FIELD32(0x08000000)
3065 #define TXWI_W0_PHYMODE FIELD32(0xc0000000)
3083 #define TXWI_W1_ACK FIELD32(0x00000001)
3084 #define TXWI_W1_NSEQ FIELD32(0x00000002)
3085 #define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
3086 #define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
3087 #define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
3088 #define TXWI_W1_PACKETID FIELD32(0xf0000000)
3089 #define TXWI_W1_PACKETID_QUEUE FIELD32(0x30000000)
3090 #define TXWI_W1_PACKETID_ENTRY FIELD32(0xc0000000)
3095 #define TXWI_W2_IV FIELD32(0xffffffff)
3100 #define TXWI_W3_EIV FIELD32(0xffffffff)
3109 #define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
3110 #define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
3111 #define RXWI_W0_BSSID FIELD32(0x00001c00)
3112 #define RXWI_W0_UDF FIELD32(0x0000e000)
3113 #define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
3114 #define RXWI_W0_TID FIELD32(0xf0000000)
3119 #define RXWI_W1_FRAG FIELD32(0x0000000f)
3120 #define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
3121 #define RXWI_W1_MCS FIELD32(0x007f0000)
3122 #define RXWI_W1_BW FIELD32(0x00800000)
3123 #define RXWI_W1_SHORT_GI FIELD32(0x01000000)
3124 #define RXWI_W1_STBC FIELD32(0x06000000)
3125 #define RXWI_W1_PHYMODE FIELD32(0xc0000000)
3130 #define RXWI_W2_RSSI0 FIELD32(0x000000ff)
3131 #define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
3132 #define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
3137 #define RXWI_W3_SNR0 FIELD32(0x000000ff)
3138 #define RXWI_W3_SNR1 FIELD32(0x0000ff00)