Lines Matching refs:rt2x00_set_field32
69 rt2x00_set_field32(®, BBPCSR_VALUE, value); in rt2500pci_bbp_write()
70 rt2x00_set_field32(®, BBPCSR_REGNUM, word); in rt2500pci_bbp_write()
71 rt2x00_set_field32(®, BBPCSR_BUSY, 1); in rt2500pci_bbp_write()
72 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1); in rt2500pci_bbp_write()
98 rt2x00_set_field32(®, BBPCSR_REGNUM, word); in rt2500pci_bbp_read()
99 rt2x00_set_field32(®, BBPCSR_BUSY, 1); in rt2500pci_bbp_read()
100 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0); in rt2500pci_bbp_read()
127 rt2x00_set_field32(®, RFCSR_VALUE, value); in rt2500pci_rf_write()
128 rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20); in rt2500pci_rf_write()
129 rt2x00_set_field32(®, RFCSR_IF_SELECT, 0); in rt2500pci_rf_write()
130 rt2x00_set_field32(®, RFCSR_BUSY, 1); in rt2500pci_rf_write()
159 rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in); in rt2500pci_eepromregister_write()
160 rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out); in rt2500pci_eepromregister_write()
161 rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK, in rt2500pci_eepromregister_write()
163 rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT, in rt2500pci_eepromregister_write()
224 rt2x00_set_field32(®, LEDCSR_LINK, enabled); in rt2500pci_brightness_set()
226 rt2x00_set_field32(®, LEDCSR_ACTIVITY, enabled); in rt2500pci_brightness_set()
240 rt2x00_set_field32(®, LEDCSR_ON_PERIOD, *delay_on); in rt2500pci_blink_set()
241 rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, *delay_off); in rt2500pci_blink_set()
274 rt2x00_set_field32(®, RXCSR0_DROP_CRC, in rt2500pci_config_filter()
276 rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL, in rt2500pci_config_filter()
278 rt2x00_set_field32(®, RXCSR0_DROP_CONTROL, in rt2500pci_config_filter()
280 rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME, in rt2500pci_config_filter()
282 rt2x00_set_field32(®, RXCSR0_DROP_TODS, in rt2500pci_config_filter()
285 rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1); in rt2500pci_config_filter()
286 rt2x00_set_field32(®, RXCSR0_DROP_MCAST, in rt2500pci_config_filter()
288 rt2x00_set_field32(®, RXCSR0_DROP_BCAST, 0); in rt2500pci_config_filter()
307 rt2x00_set_field32(®, BCNCSR1_PRELOAD, bcn_preload); in rt2500pci_config_intf()
308 rt2x00_set_field32(®, BCNCSR1_BEACON_CWMIN, queue->cw_min); in rt2500pci_config_intf()
315 rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync); in rt2500pci_config_intf()
342 rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, 0x162); in rt2500pci_config_erp()
343 rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, 0xa2); in rt2500pci_config_erp()
344 rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER); in rt2500pci_config_erp()
345 rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1); in rt2500pci_config_erp()
349 rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00); in rt2500pci_config_erp()
350 rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04); in rt2500pci_config_erp()
351 rt2x00_set_field32(®, ARCSR2_LENGTH, in rt2500pci_config_erp()
356 rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask); in rt2500pci_config_erp()
357 rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04); in rt2500pci_config_erp()
358 rt2x00_set_field32(®, ARCSR2_LENGTH, in rt2500pci_config_erp()
363 rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask); in rt2500pci_config_erp()
364 rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04); in rt2500pci_config_erp()
365 rt2x00_set_field32(®, ARCSR2_LENGTH, in rt2500pci_config_erp()
370 rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask); in rt2500pci_config_erp()
371 rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84); in rt2500pci_config_erp()
372 rt2x00_set_field32(®, ARCSR2_LENGTH, in rt2500pci_config_erp()
382 rt2x00_set_field32(®, CSR11_SLOT_TIME, erp->slot_time); in rt2500pci_config_erp()
386 rt2x00_set_field32(®, CSR18_SIFS, erp->sifs); in rt2500pci_config_erp()
387 rt2x00_set_field32(®, CSR18_PIFS, erp->pifs); in rt2500pci_config_erp()
391 rt2x00_set_field32(®, CSR19_DIFS, erp->difs); in rt2500pci_config_erp()
392 rt2x00_set_field32(®, CSR19_EIFS, erp->eifs); in rt2500pci_config_erp()
398 rt2x00_set_field32(®, CSR12_BEACON_INTERVAL, in rt2500pci_config_erp()
400 rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION, in rt2500pci_config_erp()
431 rt2x00_set_field32(®, BBPCSR1_CCK, 0); in rt2500pci_config_ant()
432 rt2x00_set_field32(®, BBPCSR1_OFDM, 0); in rt2500pci_config_ant()
437 rt2x00_set_field32(®, BBPCSR1_CCK, 2); in rt2500pci_config_ant()
438 rt2x00_set_field32(®, BBPCSR1_OFDM, 2); in rt2500pci_config_ant()
460 rt2x00_set_field32(®, BBPCSR1_CCK_FLIP, 1); in rt2500pci_config_ant()
461 rt2x00_set_field32(®, BBPCSR1_OFDM_FLIP, 1); in rt2500pci_config_ant()
469 rt2x00_set_field32(®, BBPCSR1_CCK_FLIP, 0); in rt2500pci_config_ant()
470 rt2x00_set_field32(®, BBPCSR1_OFDM_FLIP, 0); in rt2500pci_config_ant()
486 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); in rt2500pci_config_channel()
493 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1); in rt2500pci_config_channel()
494 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1); in rt2500pci_config_channel()
534 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0); in rt2500pci_config_channel()
538 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0); in rt2500pci_config_channel()
553 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); in rt2500pci_config_txpower()
563 rt2x00_set_field32(®, CSR11_LONG_RETRY, in rt2500pci_config_retry_limit()
565 rt2x00_set_field32(®, CSR11_SHORT_RETRY, in rt2500pci_config_retry_limit()
580 rt2x00_set_field32(®, CSR20_DELAY_AFTER_TBCN, in rt2500pci_config_ps()
582 rt2x00_set_field32(®, CSR20_TBCN_BEFORE_WAKEUP, in rt2500pci_config_ps()
586 rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); in rt2500pci_config_ps()
589 rt2x00_set_field32(®, CSR20_AUTOWAKE, 1); in rt2500pci_config_ps()
593 rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); in rt2500pci_config_ps()
735 rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 0); in rt2500pci_start_queue()
740 rt2x00_set_field32(®, CSR14_TSF_COUNT, 1); in rt2500pci_start_queue()
741 rt2x00_set_field32(®, CSR14_TBCN, 1); in rt2500pci_start_queue()
742 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); in rt2500pci_start_queue()
758 rt2x00_set_field32(®, TXCSR0_KICK_PRIO, 1); in rt2500pci_kick_queue()
763 rt2x00_set_field32(®, TXCSR0_KICK_TX, 1); in rt2500pci_kick_queue()
768 rt2x00_set_field32(®, TXCSR0_KICK_ATIM, 1); in rt2500pci_kick_queue()
786 rt2x00_set_field32(®, TXCSR0_ABORT, 1); in rt2500pci_stop_queue()
791 rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 1); in rt2500pci_stop_queue()
796 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); in rt2500pci_stop_queue()
797 rt2x00_set_field32(®, CSR14_TBCN, 0); in rt2500pci_stop_queue()
798 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); in rt2500pci_stop_queue()
839 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); in rt2500pci_clear_entry()
843 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); in rt2500pci_clear_entry()
847 rt2x00_set_field32(&word, TXD_W0_VALID, 0); in rt2500pci_clear_entry()
848 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); in rt2500pci_clear_entry()
862 rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); in rt2500pci_init_queues()
863 rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); in rt2500pci_init_queues()
864 rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit); in rt2500pci_init_queues()
865 rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); in rt2500pci_init_queues()
870 rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, in rt2500pci_init_queues()
876 rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, in rt2500pci_init_queues()
882 rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, in rt2500pci_init_queues()
888 rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, in rt2500pci_init_queues()
893 rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size); in rt2500pci_init_queues()
894 rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); in rt2500pci_init_queues()
899 rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, in rt2500pci_init_queues()
916 rt2x00_set_field32(®, TIMECSR_US_COUNT, 33); in rt2500pci_init_registers()
917 rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63); in rt2500pci_init_registers()
918 rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0); in rt2500pci_init_registers()
922 rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT, in rt2500pci_init_registers()
930 rt2x00_set_field32(®, CSR11_CW_SELECT, 0); in rt2500pci_init_registers()
934 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); in rt2500pci_init_registers()
935 rt2x00_set_field32(®, CSR14_TSF_SYNC, 0); in rt2500pci_init_registers()
936 rt2x00_set_field32(®, CSR14_TBCN, 0); in rt2500pci_init_registers()
937 rt2x00_set_field32(®, CSR14_TCFP, 0); in rt2500pci_init_registers()
938 rt2x00_set_field32(®, CSR14_TATIMW, 0); in rt2500pci_init_registers()
939 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); in rt2500pci_init_registers()
940 rt2x00_set_field32(®, CSR14_CFP_COUNT_PRELOAD, 0); in rt2500pci_init_registers()
941 rt2x00_set_field32(®, CSR14_TBCM_PRELOAD, 0); in rt2500pci_init_registers()
947 rt2x00_set_field32(®, TXCSR8_BBP_ID0, 10); in rt2500pci_init_registers()
948 rt2x00_set_field32(®, TXCSR8_BBP_ID0_VALID, 1); in rt2500pci_init_registers()
949 rt2x00_set_field32(®, TXCSR8_BBP_ID1, 11); in rt2500pci_init_registers()
950 rt2x00_set_field32(®, TXCSR8_BBP_ID1_VALID, 1); in rt2500pci_init_registers()
951 rt2x00_set_field32(®, TXCSR8_BBP_ID2, 13); in rt2500pci_init_registers()
952 rt2x00_set_field32(®, TXCSR8_BBP_ID2_VALID, 1); in rt2500pci_init_registers()
953 rt2x00_set_field32(®, TXCSR8_BBP_ID3, 12); in rt2500pci_init_registers()
954 rt2x00_set_field32(®, TXCSR8_BBP_ID3_VALID, 1); in rt2500pci_init_registers()
958 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_1MBS, 112); in rt2500pci_init_registers()
959 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_2MBS, 56); in rt2500pci_init_registers()
960 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_5_5MBS, 20); in rt2500pci_init_registers()
961 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_11MBS, 10); in rt2500pci_init_registers()
965 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_6MBS, 45); in rt2500pci_init_registers()
966 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_9MBS, 37); in rt2500pci_init_registers()
967 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_12MBS, 33); in rt2500pci_init_registers()
968 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_18MBS, 29); in rt2500pci_init_registers()
972 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_24MBS, 29); in rt2500pci_init_registers()
973 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_36MBS, 25); in rt2500pci_init_registers()
974 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_48MBS, 25); in rt2500pci_init_registers()
975 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_54MBS, 25); in rt2500pci_init_registers()
979 rt2x00_set_field32(®, RXCSR3_BBP_ID0, 47); /* CCK Signal */ in rt2500pci_init_registers()
980 rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1); in rt2500pci_init_registers()
981 rt2x00_set_field32(®, RXCSR3_BBP_ID1, 51); /* Rssi */ in rt2500pci_init_registers()
982 rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1); in rt2500pci_init_registers()
983 rt2x00_set_field32(®, RXCSR3_BBP_ID2, 42); /* OFDM Rate */ in rt2500pci_init_registers()
984 rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1); in rt2500pci_init_registers()
985 rt2x00_set_field32(®, RXCSR3_BBP_ID3, 51); /* RSSI */ in rt2500pci_init_registers()
986 rt2x00_set_field32(®, RXCSR3_BBP_ID3_VALID, 1); in rt2500pci_init_registers()
990 rt2x00_set_field32(®, PCICSR_BIG_ENDIAN, 0); in rt2500pci_init_registers()
991 rt2x00_set_field32(®, PCICSR_RX_TRESHOLD, 0); in rt2500pci_init_registers()
992 rt2x00_set_field32(®, PCICSR_TX_TRESHOLD, 3); in rt2500pci_init_registers()
993 rt2x00_set_field32(®, PCICSR_BURST_LENTH, 1); in rt2500pci_init_registers()
994 rt2x00_set_field32(®, PCICSR_ENABLE_CLK, 1); in rt2500pci_init_registers()
995 rt2x00_set_field32(®, PCICSR_READ_MULTIPLE, 1); in rt2500pci_init_registers()
996 rt2x00_set_field32(®, PCICSR_WRITE_INVALID, 1); in rt2500pci_init_registers()
1011 rt2x00_set_field32(®, MACCSR2_DELAY, 64); in rt2500pci_init_registers()
1015 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17); in rt2500pci_init_registers()
1016 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 26); in rt2500pci_init_registers()
1017 rt2x00_set_field32(®, RALINKCSR_AR_BBP_VALID0, 1); in rt2500pci_init_registers()
1018 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0); in rt2500pci_init_registers()
1019 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 26); in rt2500pci_init_registers()
1020 rt2x00_set_field32(®, RALINKCSR_AR_BBP_VALID1, 1); in rt2500pci_init_registers()
1028 rt2x00_set_field32(®, CSR1_SOFT_RESET, 1); in rt2500pci_init_registers()
1029 rt2x00_set_field32(®, CSR1_BBP_RESET, 0); in rt2500pci_init_registers()
1030 rt2x00_set_field32(®, CSR1_HOST_READY, 0); in rt2500pci_init_registers()
1034 rt2x00_set_field32(®, CSR1_SOFT_RESET, 0); in rt2500pci_init_registers()
1035 rt2x00_set_field32(®, CSR1_HOST_READY, 1); in rt2500pci_init_registers()
1145 rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask); in rt2500pci_toggle_irq()
1146 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask); in rt2500pci_toggle_irq()
1147 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask); in rt2500pci_toggle_irq()
1148 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask); in rt2500pci_toggle_irq()
1149 rt2x00_set_field32(®, CSR8_RXDONE, mask); in rt2500pci_toggle_irq()
1197 rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1); in rt2500pci_set_state()
1198 rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state); in rt2500pci_set_state()
1199 rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state); in rt2500pci_set_state()
1200 rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep); in rt2500pci_set_state()
1270 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); in rt2500pci_write_tx_desc()
1274 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER); in rt2500pci_write_tx_desc()
1275 rt2x00_set_field32(&word, TXD_W2_AIFS, entry->queue->aifs); in rt2500pci_write_tx_desc()
1276 rt2x00_set_field32(&word, TXD_W2_CWMIN, entry->queue->cw_min); in rt2500pci_write_tx_desc()
1277 rt2x00_set_field32(&word, TXD_W2_CWMAX, entry->queue->cw_max); in rt2500pci_write_tx_desc()
1281 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal); in rt2500pci_write_tx_desc()
1282 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service); in rt2500pci_write_tx_desc()
1283 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, in rt2500pci_write_tx_desc()
1285 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, in rt2500pci_write_tx_desc()
1290 rt2x00_set_field32(&word, TXD_W10_RTS, in rt2500pci_write_tx_desc()
1300 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); in rt2500pci_write_tx_desc()
1301 rt2x00_set_field32(&word, TXD_W0_VALID, 1); in rt2500pci_write_tx_desc()
1302 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, in rt2500pci_write_tx_desc()
1304 rt2x00_set_field32(&word, TXD_W0_ACK, in rt2500pci_write_tx_desc()
1306 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP, in rt2500pci_write_tx_desc()
1308 rt2x00_set_field32(&word, TXD_W0_OFDM, in rt2500pci_write_tx_desc()
1310 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1); in rt2500pci_write_tx_desc()
1311 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs); in rt2500pci_write_tx_desc()
1312 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, in rt2500pci_write_tx_desc()
1314 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length); in rt2500pci_write_tx_desc()
1315 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE); in rt2500pci_write_tx_desc()
1339 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); in rt2500pci_write_beacon()
1360 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); in rt2500pci_write_beacon()
1455 rt2x00_set_field32(®, irq_field, 0); in rt2500pci_enable_interrupt()
1480 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, 0); in rt2500pci_txstatus_tasklet()
1481 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, 0); in rt2500pci_txstatus_tasklet()
1482 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, 0); in rt2500pci_txstatus_tasklet()
1542 rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1); in rt2500pci_interrupt()
1543 rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1); in rt2500pci_interrupt()
1544 rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1); in rt2500pci_interrupt()
1962 rt2x00_set_field32(®, GPIOCSR_DIR0, 1); in rt2500pci_probe_hw()