Lines Matching refs:rt2x00dev
56 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev, in rt2400pci_bbp_write() argument
61 mutex_lock(&rt2x00dev->csr_mutex); in rt2400pci_bbp_write()
67 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2400pci_bbp_write()
74 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); in rt2400pci_bbp_write()
77 mutex_unlock(&rt2x00dev->csr_mutex); in rt2400pci_bbp_write()
80 static u8 rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev, in rt2400pci_bbp_read() argument
86 mutex_lock(&rt2x00dev->csr_mutex); in rt2400pci_bbp_read()
96 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2400pci_bbp_read()
102 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); in rt2400pci_bbp_read()
104 WAIT_FOR_BBP(rt2x00dev, ®); in rt2400pci_bbp_read()
109 mutex_unlock(&rt2x00dev->csr_mutex); in rt2400pci_bbp_read()
114 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev, in rt2400pci_rf_write() argument
119 mutex_lock(&rt2x00dev->csr_mutex); in rt2400pci_rf_write()
125 if (WAIT_FOR_RF(rt2x00dev, ®)) { in rt2400pci_rf_write()
132 rt2x00mmio_register_write(rt2x00dev, RFCSR, reg); in rt2400pci_rf_write()
133 rt2x00_rf_write(rt2x00dev, word, value); in rt2400pci_rf_write()
136 mutex_unlock(&rt2x00dev->csr_mutex); in rt2400pci_rf_write()
141 struct rt2x00_dev *rt2x00dev = eeprom->data; in rt2400pci_eepromregister_read() local
144 reg = rt2x00mmio_register_read(rt2x00dev, CSR21); in rt2400pci_eepromregister_read()
156 struct rt2x00_dev *rt2x00dev = eeprom->data; in rt2400pci_eepromregister_write() local
166 rt2x00mmio_register_write(rt2x00dev, CSR21, reg); in rt2400pci_eepromregister_write()
204 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev) in rt2400pci_rfkill_poll() argument
208 reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR); in rt2400pci_rfkill_poll()
221 reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR); in rt2400pci_brightness_set()
228 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); in rt2400pci_brightness_set()
239 reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR); in rt2400pci_blink_set()
242 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); in rt2400pci_blink_set()
247 static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev, in rt2400pci_init_led() argument
251 led->rt2x00dev = rt2x00dev; in rt2400pci_init_led()
262 static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev, in rt2400pci_config_filter() argument
272 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0); in rt2400pci_config_filter()
280 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags)); in rt2400pci_config_filter()
282 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags) && in rt2400pci_config_filter()
283 !rt2x00dev->intf_ap_count); in rt2400pci_config_filter()
285 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); in rt2400pci_config_filter()
288 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev, in rt2400pci_config_intf() argument
301 reg = rt2x00mmio_register_read(rt2x00dev, BCNCSR1); in rt2400pci_config_intf()
303 rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg); in rt2400pci_config_intf()
308 reg = rt2x00mmio_register_read(rt2x00dev, CSR14); in rt2400pci_config_intf()
310 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_config_intf()
314 rt2x00mmio_register_multiwrite(rt2x00dev, CSR3, in rt2400pci_config_intf()
318 rt2x00mmio_register_multiwrite(rt2x00dev, CSR5, in rt2400pci_config_intf()
323 static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev, in rt2400pci_config_erp() argument
336 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR1); in rt2400pci_config_erp()
341 rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg); in rt2400pci_config_erp()
343 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR2); in rt2400pci_config_erp()
348 rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg); in rt2400pci_config_erp()
350 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR3); in rt2400pci_config_erp()
355 rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg); in rt2400pci_config_erp()
357 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR4); in rt2400pci_config_erp()
362 rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg); in rt2400pci_config_erp()
364 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR5); in rt2400pci_config_erp()
369 rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg); in rt2400pci_config_erp()
373 rt2x00mmio_register_write(rt2x00dev, ARCSR1, erp->basic_rates); in rt2400pci_config_erp()
376 reg = rt2x00mmio_register_read(rt2x00dev, CSR11); in rt2400pci_config_erp()
378 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); in rt2400pci_config_erp()
380 reg = rt2x00mmio_register_read(rt2x00dev, CSR18); in rt2400pci_config_erp()
383 rt2x00mmio_register_write(rt2x00dev, CSR18, reg); in rt2400pci_config_erp()
385 reg = rt2x00mmio_register_read(rt2x00dev, CSR19); in rt2400pci_config_erp()
388 rt2x00mmio_register_write(rt2x00dev, CSR19, reg); in rt2400pci_config_erp()
392 reg = rt2x00mmio_register_read(rt2x00dev, CSR12); in rt2400pci_config_erp()
397 rt2x00mmio_register_write(rt2x00dev, CSR12, reg); in rt2400pci_config_erp()
401 static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev, in rt2400pci_config_ant() argument
414 r4 = rt2400pci_bbp_read(rt2x00dev, 4); in rt2400pci_config_ant()
415 r1 = rt2400pci_bbp_read(rt2x00dev, 1); in rt2400pci_config_ant()
449 rt2400pci_bbp_write(rt2x00dev, 4, r4); in rt2400pci_config_ant()
450 rt2400pci_bbp_write(rt2x00dev, 1, r1); in rt2400pci_config_ant()
453 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev, in rt2400pci_config_channel() argument
462 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1); in rt2400pci_config_channel()
463 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2); in rt2400pci_config_channel()
464 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3); in rt2400pci_config_channel()
469 if (rt2x00_rf(rt2x00dev, RF2420)) in rt2400pci_config_channel()
477 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1); in rt2400pci_config_channel()
478 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32); in rt2400pci_config_channel()
479 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3); in rt2400pci_config_channel()
483 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1); in rt2400pci_config_channel()
484 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2); in rt2400pci_config_channel()
485 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3); in rt2400pci_config_channel()
495 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1); in rt2400pci_config_channel()
496 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3); in rt2400pci_config_channel()
501 rf->rf1 = rt2x00mmio_register_read(rt2x00dev, CNT0); in rt2400pci_config_channel()
504 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower) in rt2400pci_config_txpower() argument
506 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower)); in rt2400pci_config_txpower()
509 static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev, in rt2400pci_config_retry_limit() argument
514 reg = rt2x00mmio_register_read(rt2x00dev, CSR11); in rt2400pci_config_retry_limit()
519 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); in rt2400pci_config_retry_limit()
522 static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev, in rt2400pci_config_ps() argument
531 reg = rt2x00mmio_register_read(rt2x00dev, CSR20); in rt2400pci_config_ps()
533 (rt2x00dev->beacon_int - 20) * 16); in rt2400pci_config_ps()
539 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); in rt2400pci_config_ps()
542 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); in rt2400pci_config_ps()
544 reg = rt2x00mmio_register_read(rt2x00dev, CSR20); in rt2400pci_config_ps()
546 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); in rt2400pci_config_ps()
549 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); in rt2400pci_config_ps()
552 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev, in rt2400pci_config() argument
557 rt2400pci_config_channel(rt2x00dev, &libconf->rf); in rt2400pci_config()
559 rt2400pci_config_txpower(rt2x00dev, in rt2400pci_config()
562 rt2400pci_config_retry_limit(rt2x00dev, libconf); in rt2400pci_config()
564 rt2400pci_config_ps(rt2x00dev, libconf); in rt2400pci_config()
567 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev, in rt2400pci_config_cw() argument
572 reg = rt2x00mmio_register_read(rt2x00dev, CSR11); in rt2400pci_config_cw()
575 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); in rt2400pci_config_cw()
581 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev, in rt2400pci_link_stats() argument
590 reg = rt2x00mmio_register_read(rt2x00dev, CNT0); in rt2400pci_link_stats()
596 bbp = rt2400pci_bbp_read(rt2x00dev, 39); in rt2400pci_link_stats()
600 static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev, in rt2400pci_set_vgc() argument
604 rt2400pci_bbp_write(rt2x00dev, 13, vgc_level); in rt2400pci_set_vgc()
610 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev, in rt2400pci_reset_tuner() argument
613 rt2400pci_set_vgc(rt2x00dev, qual, 0x08); in rt2400pci_reset_tuner()
616 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev, in rt2400pci_link_tuner() argument
630 rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level); in rt2400pci_link_tuner()
632 rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level); in rt2400pci_link_tuner()
640 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; in rt2400pci_start_queue() local
645 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0); in rt2400pci_start_queue()
647 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); in rt2400pci_start_queue()
650 reg = rt2x00mmio_register_read(rt2x00dev, CSR14); in rt2400pci_start_queue()
654 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_start_queue()
663 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; in rt2400pci_kick_queue() local
668 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0); in rt2400pci_kick_queue()
670 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2400pci_kick_queue()
673 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0); in rt2400pci_kick_queue()
675 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2400pci_kick_queue()
678 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0); in rt2400pci_kick_queue()
680 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2400pci_kick_queue()
689 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; in rt2400pci_stop_queue() local
696 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0); in rt2400pci_stop_queue()
698 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2400pci_stop_queue()
701 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0); in rt2400pci_stop_queue()
703 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); in rt2400pci_stop_queue()
706 reg = rt2x00mmio_register_read(rt2x00dev, CSR14); in rt2400pci_stop_queue()
710 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_stop_queue()
715 tasklet_kill(&rt2x00dev->tbtt_tasklet); in rt2400pci_stop_queue()
768 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev) in rt2400pci_init_queues() argument
776 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR2); in rt2400pci_init_queues()
777 rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); in rt2400pci_init_queues()
778 rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); in rt2400pci_init_queues()
779 rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit); in rt2400pci_init_queues()
780 rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); in rt2400pci_init_queues()
781 rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg); in rt2400pci_init_queues()
783 entry_priv = rt2x00dev->tx[1].entries[0].priv_data; in rt2400pci_init_queues()
784 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR3); in rt2400pci_init_queues()
787 rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg); in rt2400pci_init_queues()
789 entry_priv = rt2x00dev->tx[0].entries[0].priv_data; in rt2400pci_init_queues()
790 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR5); in rt2400pci_init_queues()
793 rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg); in rt2400pci_init_queues()
795 entry_priv = rt2x00dev->atim->entries[0].priv_data; in rt2400pci_init_queues()
796 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR4); in rt2400pci_init_queues()
799 rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg); in rt2400pci_init_queues()
801 entry_priv = rt2x00dev->bcn->entries[0].priv_data; in rt2400pci_init_queues()
802 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR6); in rt2400pci_init_queues()
805 rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg); in rt2400pci_init_queues()
807 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR1); in rt2400pci_init_queues()
808 rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size); in rt2400pci_init_queues()
809 rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); in rt2400pci_init_queues()
810 rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg); in rt2400pci_init_queues()
812 entry_priv = rt2x00dev->rx->entries[0].priv_data; in rt2400pci_init_queues()
813 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR2); in rt2400pci_init_queues()
816 rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg); in rt2400pci_init_queues()
821 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev) in rt2400pci_init_registers() argument
825 rt2x00mmio_register_write(rt2x00dev, PSCSR0, 0x00020002); in rt2400pci_init_registers()
826 rt2x00mmio_register_write(rt2x00dev, PSCSR1, 0x00000002); in rt2400pci_init_registers()
827 rt2x00mmio_register_write(rt2x00dev, PSCSR2, 0x00023f20); in rt2400pci_init_registers()
828 rt2x00mmio_register_write(rt2x00dev, PSCSR3, 0x00000002); in rt2400pci_init_registers()
830 reg = rt2x00mmio_register_read(rt2x00dev, TIMECSR); in rt2400pci_init_registers()
834 rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg); in rt2400pci_init_registers()
836 reg = rt2x00mmio_register_read(rt2x00dev, CSR9); in rt2400pci_init_registers()
838 (rt2x00dev->rx->data_size / 128)); in rt2400pci_init_registers()
839 rt2x00mmio_register_write(rt2x00dev, CSR9, reg); in rt2400pci_init_registers()
841 reg = rt2x00mmio_register_read(rt2x00dev, CSR14); in rt2400pci_init_registers()
850 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_init_registers()
852 rt2x00mmio_register_write(rt2x00dev, CNT3, 0x3f080000); in rt2400pci_init_registers()
854 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR0); in rt2400pci_init_registers()
859 rt2x00mmio_register_write(rt2x00dev, ARCSR0, reg); in rt2400pci_init_registers()
861 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR3); in rt2400pci_init_registers()
868 rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg); in rt2400pci_init_registers()
870 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100); in rt2400pci_init_registers()
872 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) in rt2400pci_init_registers()
875 rt2x00mmio_register_write(rt2x00dev, MACCSR0, 0x00217223); in rt2400pci_init_registers()
876 rt2x00mmio_register_write(rt2x00dev, MACCSR1, 0x00235518); in rt2400pci_init_registers()
878 reg = rt2x00mmio_register_read(rt2x00dev, MACCSR2); in rt2400pci_init_registers()
880 rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg); in rt2400pci_init_registers()
882 reg = rt2x00mmio_register_read(rt2x00dev, RALINKCSR); in rt2400pci_init_registers()
887 rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg); in rt2400pci_init_registers()
889 reg = rt2x00mmio_register_read(rt2x00dev, CSR1); in rt2400pci_init_registers()
893 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); in rt2400pci_init_registers()
895 reg = rt2x00mmio_register_read(rt2x00dev, CSR1); in rt2400pci_init_registers()
898 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); in rt2400pci_init_registers()
905 reg = rt2x00mmio_register_read(rt2x00dev, CNT0); in rt2400pci_init_registers()
906 reg = rt2x00mmio_register_read(rt2x00dev, CNT4); in rt2400pci_init_registers()
911 static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) in rt2400pci_wait_bbp_ready() argument
917 value = rt2400pci_bbp_read(rt2x00dev, 0); in rt2400pci_wait_bbp_ready()
923 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n"); in rt2400pci_wait_bbp_ready()
927 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev) in rt2400pci_init_bbp() argument
934 if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev))) in rt2400pci_init_bbp()
937 rt2400pci_bbp_write(rt2x00dev, 1, 0x00); in rt2400pci_init_bbp()
938 rt2400pci_bbp_write(rt2x00dev, 3, 0x27); in rt2400pci_init_bbp()
939 rt2400pci_bbp_write(rt2x00dev, 4, 0x08); in rt2400pci_init_bbp()
940 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f); in rt2400pci_init_bbp()
941 rt2400pci_bbp_write(rt2x00dev, 15, 0x72); in rt2400pci_init_bbp()
942 rt2400pci_bbp_write(rt2x00dev, 16, 0x74); in rt2400pci_init_bbp()
943 rt2400pci_bbp_write(rt2x00dev, 17, 0x20); in rt2400pci_init_bbp()
944 rt2400pci_bbp_write(rt2x00dev, 18, 0x72); in rt2400pci_init_bbp()
945 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b); in rt2400pci_init_bbp()
946 rt2400pci_bbp_write(rt2x00dev, 20, 0x00); in rt2400pci_init_bbp()
947 rt2400pci_bbp_write(rt2x00dev, 28, 0x11); in rt2400pci_init_bbp()
948 rt2400pci_bbp_write(rt2x00dev, 29, 0x04); in rt2400pci_init_bbp()
949 rt2400pci_bbp_write(rt2x00dev, 30, 0x21); in rt2400pci_init_bbp()
950 rt2400pci_bbp_write(rt2x00dev, 31, 0x00); in rt2400pci_init_bbp()
953 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i); in rt2400pci_init_bbp()
958 rt2400pci_bbp_write(rt2x00dev, reg_id, value); in rt2400pci_init_bbp()
968 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev, in rt2400pci_toggle_irq() argument
980 reg = rt2x00mmio_register_read(rt2x00dev, CSR7); in rt2400pci_toggle_irq()
981 rt2x00mmio_register_write(rt2x00dev, CSR7, reg); in rt2400pci_toggle_irq()
988 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags); in rt2400pci_toggle_irq()
990 reg = rt2x00mmio_register_read(rt2x00dev, CSR8); in rt2400pci_toggle_irq()
996 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2400pci_toggle_irq()
998 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags); in rt2400pci_toggle_irq()
1005 tasklet_kill(&rt2x00dev->txstatus_tasklet); in rt2400pci_toggle_irq()
1006 tasklet_kill(&rt2x00dev->rxdone_tasklet); in rt2400pci_toggle_irq()
1007 tasklet_kill(&rt2x00dev->tbtt_tasklet); in rt2400pci_toggle_irq()
1011 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev) in rt2400pci_enable_radio() argument
1016 if (unlikely(rt2400pci_init_queues(rt2x00dev) || in rt2400pci_enable_radio()
1017 rt2400pci_init_registers(rt2x00dev) || in rt2400pci_enable_radio()
1018 rt2400pci_init_bbp(rt2x00dev))) in rt2400pci_enable_radio()
1024 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev) in rt2400pci_disable_radio() argument
1029 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0); in rt2400pci_disable_radio()
1032 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev, in rt2400pci_set_state() argument
1043 reg = rt2x00mmio_register_read(rt2x00dev, PWRCSR1); in rt2400pci_set_state()
1048 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); in rt2400pci_set_state()
1056 reg2 = rt2x00mmio_register_read(rt2x00dev, PWRCSR1); in rt2400pci_set_state()
1061 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); in rt2400pci_set_state()
1068 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev, in rt2400pci_set_device_state() argument
1075 retval = rt2400pci_enable_radio(rt2x00dev); in rt2400pci_set_device_state()
1078 rt2400pci_disable_radio(rt2x00dev); in rt2400pci_set_device_state()
1082 rt2400pci_toggle_irq(rt2x00dev, state); in rt2400pci_set_device_state()
1088 retval = rt2400pci_set_state(rt2x00dev, state); in rt2400pci_set_device_state()
1096 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n", in rt2400pci_set_device_state()
1179 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; in rt2400pci_write_beacon() local
1186 reg = rt2x00mmio_register_read(rt2x00dev, CSR14); in rt2400pci_write_beacon()
1188 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_write_beacon()
1191 rt2x00_err(rt2x00dev, "Fail to map beacon, aborting\n"); in rt2400pci_write_beacon()
1206 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry); in rt2400pci_write_beacon()
1212 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_write_beacon()
1221 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; in rt2400pci_fill_rxdone() local
1250 tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw, NULL); in rt2400pci_fill_rxdone()
1265 entry->queue->rt2x00dev->rssi_offset; in rt2400pci_fill_rxdone()
1276 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, in rt2400pci_txdone() argument
1279 struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); in rt2400pci_txdone()
1315 static inline void rt2400pci_enable_interrupt(struct rt2x00_dev *rt2x00dev, in rt2400pci_enable_interrupt() argument
1324 spin_lock_irq(&rt2x00dev->irqmask_lock); in rt2400pci_enable_interrupt()
1326 reg = rt2x00mmio_register_read(rt2x00dev, CSR8); in rt2400pci_enable_interrupt()
1328 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2400pci_enable_interrupt()
1330 spin_unlock_irq(&rt2x00dev->irqmask_lock); in rt2400pci_enable_interrupt()
1335 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; in rt2400pci_txstatus_tasklet() local
1341 rt2400pci_txdone(rt2x00dev, QID_ATIM); in rt2400pci_txstatus_tasklet()
1342 rt2400pci_txdone(rt2x00dev, QID_AC_VO); in rt2400pci_txstatus_tasklet()
1343 rt2400pci_txdone(rt2x00dev, QID_AC_VI); in rt2400pci_txstatus_tasklet()
1348 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) { in rt2400pci_txstatus_tasklet()
1349 spin_lock_irq(&rt2x00dev->irqmask_lock); in rt2400pci_txstatus_tasklet()
1351 reg = rt2x00mmio_register_read(rt2x00dev, CSR8); in rt2400pci_txstatus_tasklet()
1355 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2400pci_txstatus_tasklet()
1357 spin_unlock_irq(&rt2x00dev->irqmask_lock); in rt2400pci_txstatus_tasklet()
1363 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; in rt2400pci_tbtt_tasklet() local
1364 rt2x00lib_beacondone(rt2x00dev); in rt2400pci_tbtt_tasklet()
1365 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt2400pci_tbtt_tasklet()
1366 rt2400pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE); in rt2400pci_tbtt_tasklet()
1371 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; in rt2400pci_rxdone_tasklet() local
1372 if (rt2x00mmio_rxdone(rt2x00dev)) in rt2400pci_rxdone_tasklet()
1373 tasklet_schedule(&rt2x00dev->rxdone_tasklet); in rt2400pci_rxdone_tasklet()
1374 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt2400pci_rxdone_tasklet()
1375 rt2400pci_enable_interrupt(rt2x00dev, CSR8_RXDONE); in rt2400pci_rxdone_tasklet()
1380 struct rt2x00_dev *rt2x00dev = dev_instance; in rt2400pci_interrupt() local
1387 reg = rt2x00mmio_register_read(rt2x00dev, CSR7); in rt2400pci_interrupt()
1388 rt2x00mmio_register_write(rt2x00dev, CSR7, reg); in rt2400pci_interrupt()
1393 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt2400pci_interrupt()
1402 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet); in rt2400pci_interrupt()
1405 tasklet_schedule(&rt2x00dev->rxdone_tasklet); in rt2400pci_interrupt()
1410 tasklet_schedule(&rt2x00dev->txstatus_tasklet); in rt2400pci_interrupt()
1423 spin_lock(&rt2x00dev->irqmask_lock); in rt2400pci_interrupt()
1425 reg = rt2x00mmio_register_read(rt2x00dev, CSR8); in rt2400pci_interrupt()
1427 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2400pci_interrupt()
1429 spin_unlock(&rt2x00dev->irqmask_lock); in rt2400pci_interrupt()
1439 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev) in rt2400pci_validate_eeprom() argument
1446 reg = rt2x00mmio_register_read(rt2x00dev, CSR21); in rt2400pci_validate_eeprom()
1448 eeprom.data = rt2x00dev; in rt2400pci_validate_eeprom()
1458 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom, in rt2400pci_validate_eeprom()
1464 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); in rt2400pci_validate_eeprom()
1465 rt2x00lib_set_mac_address(rt2x00dev, mac); in rt2400pci_validate_eeprom()
1467 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA); in rt2400pci_validate_eeprom()
1469 rt2x00_err(rt2x00dev, "Invalid EEPROM data detected\n"); in rt2400pci_validate_eeprom()
1476 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev) in rt2400pci_init_eeprom() argument
1485 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA); in rt2400pci_init_eeprom()
1491 reg = rt2x00mmio_register_read(rt2x00dev, CSR0); in rt2400pci_init_eeprom()
1492 rt2x00_set_chip(rt2x00dev, RT2460, value, in rt2400pci_init_eeprom()
1495 if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) { in rt2400pci_init_eeprom()
1496 rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n"); in rt2400pci_init_eeprom()
1503 rt2x00dev->default_ant.tx = in rt2400pci_init_eeprom()
1505 rt2x00dev->default_ant.rx = in rt2400pci_init_eeprom()
1514 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY) in rt2400pci_init_eeprom()
1515 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; in rt2400pci_init_eeprom()
1516 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY) in rt2400pci_init_eeprom()
1517 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; in rt2400pci_init_eeprom()
1525 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); in rt2400pci_init_eeprom()
1529 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual, in rt2400pci_init_eeprom()
1537 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); in rt2400pci_init_eeprom()
1543 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); in rt2400pci_init_eeprom()
1569 static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) in rt2400pci_probe_hw_mode() argument
1571 struct hw_mode_spec *spec = &rt2x00dev->spec; in rt2400pci_probe_hw_mode()
1579 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK); in rt2400pci_probe_hw_mode()
1580 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS); in rt2400pci_probe_hw_mode()
1581 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING); in rt2400pci_probe_hw_mode()
1582 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM); in rt2400pci_probe_hw_mode()
1584 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); in rt2400pci_probe_hw_mode()
1585 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, in rt2400pci_probe_hw_mode()
1586 rt2x00_eeprom_addr(rt2x00dev, in rt2400pci_probe_hw_mode()
1607 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START); in rt2400pci_probe_hw_mode()
1616 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev) in rt2400pci_probe_hw() argument
1624 retval = rt2400pci_validate_eeprom(rt2x00dev); in rt2400pci_probe_hw()
1628 retval = rt2400pci_init_eeprom(rt2x00dev); in rt2400pci_probe_hw()
1636 reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR); in rt2400pci_probe_hw()
1638 rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg); in rt2400pci_probe_hw()
1643 retval = rt2400pci_probe_hw_mode(rt2x00dev); in rt2400pci_probe_hw()
1650 __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags); in rt2400pci_probe_hw()
1651 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags); in rt2400pci_probe_hw()
1652 __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags); in rt2400pci_probe_hw()
1657 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; in rt2400pci_probe_hw()
1669 struct rt2x00_dev *rt2x00dev = hw->priv; in rt2400pci_conf_tx() local
1685 rt2400pci_config_cw(rt2x00dev, in rt2400pci_conf_tx()
1686 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max); in rt2400pci_conf_tx()
1694 struct rt2x00_dev *rt2x00dev = hw->priv; in rt2400pci_get_tsf() local
1698 reg = rt2x00mmio_register_read(rt2x00dev, CSR17); in rt2400pci_get_tsf()
1700 reg = rt2x00mmio_register_read(rt2x00dev, CSR16); in rt2400pci_get_tsf()
1708 struct rt2x00_dev *rt2x00dev = hw->priv; in rt2400pci_tx_last_beacon() local
1711 reg = rt2x00mmio_register_read(rt2x00dev, CSR15); in rt2400pci_tx_last_beacon()