44 	mt7601u_wr(dev, MT_RF_CSR_CFG,  in mt7601u_rf_wr()
78 	mt7601u_wr(dev, MT_RF_CSR_CFG,  in mt7601u_rf_rr()
143 	mt7601u_wr(dev, MT_BBP_CSR_CFG,  in mt7601u_bbp_wr()
167 	mt7601u_wr(dev, MT_BBP_CSR_CFG,  in mt7601u_bbp_rr()
437 	mt7601u_wr(dev, MT_TX_PWR_CFG_0, int_to_s6(t->ofdm[1].bw20) << 24 |  in __mt7601u_phy_set_channel()
509 	mt7601u_wr(dev, MT_RF_BYPASS_0, 0);  in mt7601u_read_bootup_temp()
510 	mt7601u_wr(dev, MT_RF_SETTING_0, 0x00000010);  in mt7601u_read_bootup_temp()
511 	mt7601u_wr(dev, MT_RF_BYPASS_0, 0x00000010);  in mt7601u_read_bootup_temp()
530 	mt7601u_wr(dev, MT_RF_BYPASS_0, 0);  in mt7601u_read_bootup_temp()
531 	mt7601u_wr(dev, MT_RF_SETTING_0, rf_set);  in mt7601u_read_bootup_temp()
532 	mt7601u_wr(dev, MT_RF_BYPASS_0, rf_bp);  in mt7601u_read_bootup_temp()
568 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX);  in mt7601u_rxdc_cal()
585 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0);  in mt7601u_rxdc_cal()
592 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, mac_ctrl);  in mt7601u_rxdc_cal()
653 	mt7601u_wr(dev, MT_RF_SETTING_0, 0x00000030);  in mt7601u_tssi_dc_gain_cal()
654 	mt7601u_wr(dev, MT_RF_BYPASS_0, 0x000c0030);  in mt7601u_tssi_dc_gain_cal()
655 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0);  in mt7601u_tssi_dc_gain_cal()
717 	mt7601u_wr(dev, MT_RF_BYPASS_0, 0);  in mt7601u_tssi_dc_gain_cal()
718 	mt7601u_wr(dev, MT_RF_SETTING_0, 0);  in mt7601u_tssi_dc_gain_cal()
948 	mt7601u_wr(dev, MT_TX_ALC_CFG_1, val);  in mt7601u_tssi_cal()
1175 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, mac_ctrl);  in mt7601u_init_cal()
1197 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, val);  in mt7601u_bbp_set_bw()
1203 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, old);  in mt7601u_bbp_set_bw()