24 static void mt7601u_agc_reset(struct mt7601u_dev *dev);
27 mt7601u_rf_wr(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 value)  in mt7601u_rf_wr()  argument
31 	if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)) ||  in mt7601u_rf_wr()
34 	if (test_bit(MT7601U_STATE_REMOVED, &dev->state))  in mt7601u_rf_wr()
37 	mutex_lock(&dev->reg_atomic_mutex);  in mt7601u_rf_wr()
39 	if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) {  in mt7601u_rf_wr()
44 	mt7601u_wr(dev, MT_RF_CSR_CFG,  in mt7601u_rf_wr()
50 	trace_rf_write(dev, bank, offset, value);  in mt7601u_rf_wr()
52 	mutex_unlock(&dev->reg_atomic_mutex);  in mt7601u_rf_wr()
55 		dev_err(dev->dev, "Error: RF write %02hhx:%02hhx failed:%d!!\n",  in mt7601u_rf_wr()
62 mt7601u_rf_rr(struct mt7601u_dev *dev, u8 bank, u8 offset)  in mt7601u_rf_rr()  argument
67 	if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)) ||  in mt7601u_rf_rr()
70 	if (test_bit(MT7601U_STATE_REMOVED, &dev->state))  in mt7601u_rf_rr()
73 	mutex_lock(&dev->reg_atomic_mutex);  in mt7601u_rf_rr()
75 	if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100))  in mt7601u_rf_rr()
78 	mt7601u_wr(dev, MT_RF_CSR_CFG,  in mt7601u_rf_rr()
83 	if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100))  in mt7601u_rf_rr()
86 	val = mt7601u_rr(dev, MT_RF_CSR_CFG);  in mt7601u_rf_rr()
90 		trace_rf_read(dev, bank, offset, ret);  in mt7601u_rf_rr()
93 	mutex_unlock(&dev->reg_atomic_mutex);  in mt7601u_rf_rr()
96 		dev_err(dev->dev, "Error: RF read %02hhx:%02hhx failed:%d!!\n",  in mt7601u_rf_rr()
103 mt7601u_rf_rmw(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 mask, u8 val)  in mt7601u_rf_rmw()  argument
107 	ret = mt7601u_rf_rr(dev, bank, offset);  in mt7601u_rf_rmw()
111 	ret = mt7601u_rf_wr(dev, bank, offset, val);  in mt7601u_rf_rmw()
119 mt7601u_rf_set(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 val)  in mt7601u_rf_set()  argument
121 	return mt7601u_rf_rmw(dev, bank, offset, 0, val);  in mt7601u_rf_set()
125 mt7601u_rf_clear(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 mask)  in mt7601u_rf_clear()  argument
127 	return mt7601u_rf_rmw(dev, bank, offset, mask, 0);  in mt7601u_rf_clear()
130 static void mt7601u_bbp_wr(struct mt7601u_dev *dev, u8 offset, u8 val)  in mt7601u_bbp_wr()  argument
132 	if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)) ||  in mt7601u_bbp_wr()
133 	    test_bit(MT7601U_STATE_REMOVED, &dev->state))  in mt7601u_bbp_wr()
136 	mutex_lock(&dev->reg_atomic_mutex);  in mt7601u_bbp_wr()
138 	if (!mt76_poll(dev, MT_BBP_CSR_CFG, MT_BBP_CSR_CFG_BUSY, 0, 1000)) {  in mt7601u_bbp_wr()
139 		dev_err(dev->dev, "Error: BBP write %02hhx failed!!\n", offset);  in mt7601u_bbp_wr()
143 	mt7601u_wr(dev, MT_BBP_CSR_CFG,  in mt7601u_bbp_wr()
147 	trace_bbp_write(dev, offset, val);  in mt7601u_bbp_wr()
149 	mutex_unlock(&dev->reg_atomic_mutex);  in mt7601u_bbp_wr()
152 static int mt7601u_bbp_rr(struct mt7601u_dev *dev, u8 offset)  in mt7601u_bbp_rr()  argument
157 	if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)))  in mt7601u_bbp_rr()
159 	if (test_bit(MT7601U_STATE_REMOVED, &dev->state))  in mt7601u_bbp_rr()
162 	mutex_lock(&dev->reg_atomic_mutex);  in mt7601u_bbp_rr()
164 	if (!mt76_poll(dev, MT_BBP_CSR_CFG, MT_BBP_CSR_CFG_BUSY, 0, 1000))  in mt7601u_bbp_rr()
167 	mt7601u_wr(dev, MT_BBP_CSR_CFG,  in mt7601u_bbp_rr()
172 	if (!mt76_poll(dev, MT_BBP_CSR_CFG, MT_BBP_CSR_CFG_BUSY, 0, 1000))  in mt7601u_bbp_rr()
175 	val = mt7601u_rr(dev, MT_BBP_CSR_CFG);  in mt7601u_bbp_rr()
178 		trace_bbp_read(dev, offset, ret);  in mt7601u_bbp_rr()
181 	mutex_unlock(&dev->reg_atomic_mutex);  in mt7601u_bbp_rr()
184 		dev_err(dev->dev, "Error: BBP read %02hhx failed:%d!!\n",  in mt7601u_bbp_rr()
190 static int mt7601u_bbp_rmw(struct mt7601u_dev *dev, u8 offset, u8 mask, u8 val)  in mt7601u_bbp_rmw()  argument
194 	ret = mt7601u_bbp_rr(dev, offset);  in mt7601u_bbp_rmw()
198 	mt7601u_bbp_wr(dev, offset, val);  in mt7601u_bbp_rmw()
203 static u8 mt7601u_bbp_rmc(struct mt7601u_dev *dev, u8 offset, u8 mask, u8 val)  in mt7601u_bbp_rmc()  argument
207 	ret = mt7601u_bbp_rr(dev, offset);  in mt7601u_bbp_rmc()
212 		mt7601u_bbp_wr(dev, offset, val);  in mt7601u_bbp_rmc()
217 int mt7601u_wait_bbp_ready(struct mt7601u_dev *dev)  in mt7601u_wait_bbp_ready()  argument
223 		val = mt7601u_bbp_rr(dev, MT_BBP_REG_VERSION);  in mt7601u_wait_bbp_ready()
229 		dev_err(dev->dev, "Error: BBP is not ready\n");  in mt7601u_wait_bbp_ready()
236 u32 mt7601u_bbp_set_ctrlch(struct mt7601u_dev *dev, bool below)  in mt7601u_bbp_set_ctrlch()  argument
238 	return mt7601u_bbp_rmc(dev, 3, 0x20, below ? 0x20 : 0);  in mt7601u_bbp_set_ctrlch()
241 int mt7601u_phy_get_rssi(struct mt7601u_dev *dev,  in mt7601u_phy_get_rssi()  argument
265 	val -= dev->ee->lna_gain;  in mt7601u_phy_get_rssi()
266 	val -= dev->ee->rssi_offset[0];  in mt7601u_phy_get_rssi()
271 static void mt7601u_vco_cal(struct mt7601u_dev *dev)  in mt7601u_vco_cal()  argument
273 	mt7601u_rf_wr(dev, 0, 4, 0x0a);  in mt7601u_vco_cal()
274 	mt7601u_rf_wr(dev, 0, 5, 0x20);  in mt7601u_vco_cal()
275 	mt7601u_rf_set(dev, 0, 4, BIT(7));  in mt7601u_vco_cal()
279 static int mt7601u_set_bw_filter(struct mt7601u_dev *dev, bool cal)  in mt7601u_set_bw_filter()  argument
286 	if (dev->bw != MT_BW_20)  in mt7601u_set_bw_filter()
290 	ret = mt7601u_mcu_calibrate(dev, MCU_CAL_BW, filter | 1);  in mt7601u_set_bw_filter()
294 	return mt7601u_mcu_calibrate(dev, MCU_CAL_BW, filter);  in mt7601u_set_bw_filter()
297 static int mt7601u_load_bbp_temp_table_bw(struct mt7601u_dev *dev)  in mt7601u_load_bbp_temp_table_bw()  argument
301 	if (WARN_ON(dev->temp_mode > MT_TEMP_MODE_LOW))  in mt7601u_load_bbp_temp_table_bw()
304 	t = &bbp_mode_table[dev->temp_mode][dev->bw];  in mt7601u_load_bbp_temp_table_bw()
306 	return mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, t->regs, t->n);  in mt7601u_load_bbp_temp_table_bw()
309 static int mt7601u_bbp_temp(struct mt7601u_dev *dev, int mode, const char *name)  in mt7601u_bbp_temp()  argument
314 	if (dev->temp_mode == mode)  in mt7601u_bbp_temp()
317 	dev->temp_mode = mode;  in mt7601u_bbp_temp()
318 	trace_temp_mode(dev, mode);  in mt7601u_bbp_temp()
320 	t = bbp_mode_table[dev->temp_mode];  in mt7601u_bbp_temp()
321 	ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP,  in mt7601u_bbp_temp()
326 	return mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP,  in mt7601u_bbp_temp()
327 				       t[dev->bw].regs, t[dev->bw].n);  in mt7601u_bbp_temp()
330 static void mt7601u_apply_ch14_fixup(struct mt7601u_dev *dev, int hw_chan)  in mt7601u_apply_ch14_fixup()  argument
332 	struct mt7601u_rate_power *t = &dev->ee->power_rate_table;  in mt7601u_apply_ch14_fixup()
334 	if (hw_chan != 14 || dev->bw != MT_BW_20) {  in mt7601u_apply_ch14_fixup()
335 		mt7601u_bbp_rmw(dev, 4, 0x20, 0);  in mt7601u_apply_ch14_fixup()
336 		mt7601u_bbp_wr(dev, 178, 0xff);  in mt7601u_apply_ch14_fixup()
338 		t->cck[0].bw20 = dev->ee->real_cck_bw20[0];  in mt7601u_apply_ch14_fixup()
339 		t->cck[1].bw20 = dev->ee->real_cck_bw20[1];  in mt7601u_apply_ch14_fixup()
341 		mt7601u_bbp_wr(dev, 4, 0x60);  in mt7601u_apply_ch14_fixup()
342 		mt7601u_bbp_wr(dev, 178, 0);  in mt7601u_apply_ch14_fixup()
345 		t->cck[0].bw20 = dev->ee->real_cck_bw20[0] - 2;  in mt7601u_apply_ch14_fixup()
346 		t->cck[1].bw20 = dev->ee->real_cck_bw20[1] - 2;  in mt7601u_apply_ch14_fixup()
350 static int __mt7601u_phy_set_channel(struct mt7601u_dev *dev,  in __mt7601u_phy_set_channel()  argument
374 		{ 62, 0x37 - dev->ee->lna_gain },  in __mt7601u_phy_set_channel()
375 		{ 63, 0x37 - dev->ee->lna_gain },  in __mt7601u_phy_set_channel()
376 		{ 64, 0x37 - dev->ee->lna_gain },  in __mt7601u_phy_set_channel()
382 	struct mt7601u_rate_power *t = &dev->ee->power_rate_table;  in __mt7601u_phy_set_channel()
400 			dev_err(dev->dev, "Error: invalid 40MHz channel!!\n");  in __mt7601u_phy_set_channel()
403 	if (bw != dev->bw || chan_ext_below != dev->chan_ext_below) {  in __mt7601u_phy_set_channel()
404 		dev_dbg(dev->dev, "Info: switching HT mode bw:%d below:%d\n",  in __mt7601u_phy_set_channel()
407 		mt7601u_bbp_set_bw(dev, bw);  in __mt7601u_phy_set_channel()
409 		mt7601u_bbp_set_ctrlch(dev, chan_ext_below);  in __mt7601u_phy_set_channel()
410 		mt7601u_mac_set_ctrlch(dev, chan_ext_below);  in __mt7601u_phy_set_channel()
411 		dev->chan_ext_below = chan_ext_below;  in __mt7601u_phy_set_channel()
417 	ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_RF,  in __mt7601u_phy_set_channel()
422 	mt7601u_rmw(dev, MT_TX_ALC_CFG_0, 0x3f3f,  in __mt7601u_phy_set_channel()
423 		    dev->ee->chan_pwr[chan_idx] & 0x3f);  in __mt7601u_phy_set_channel()
425 	ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP,  in __mt7601u_phy_set_channel()
430 	mt7601u_vco_cal(dev);  in __mt7601u_phy_set_channel()
431 	mt7601u_bbp_set_bw(dev, bw);  in __mt7601u_phy_set_channel()
432 	ret = mt7601u_set_bw_filter(dev, false);  in __mt7601u_phy_set_channel()
436 	mt7601u_apply_ch14_fixup(dev, chan->hw_value);  in __mt7601u_phy_set_channel()
437 	mt7601u_wr(dev, MT_TX_PWR_CFG_0, int_to_s6(t->ofdm[1].bw20) << 24 |  in __mt7601u_phy_set_channel()
442 	if (test_bit(MT7601U_STATE_SCANNING, &dev->state))  in __mt7601u_phy_set_channel()
443 		mt7601u_agc_reset(dev);  in __mt7601u_phy_set_channel()
445 	dev->chandef = *chandef;  in __mt7601u_phy_set_channel()
450 int mt7601u_phy_set_channel(struct mt7601u_dev *dev,  in mt7601u_phy_set_channel()  argument
455 	cancel_delayed_work_sync(&dev->cal_work);  in mt7601u_phy_set_channel()
456 	cancel_delayed_work_sync(&dev->freq_cal.work);  in mt7601u_phy_set_channel()
458 	mutex_lock(&dev->hw_atomic_mutex);  in mt7601u_phy_set_channel()
459 	ret = __mt7601u_phy_set_channel(dev, chandef);  in mt7601u_phy_set_channel()
460 	mutex_unlock(&dev->hw_atomic_mutex);  in mt7601u_phy_set_channel()
464 	if (test_bit(MT7601U_STATE_SCANNING, &dev->state))  in mt7601u_phy_set_channel()
467 	ieee80211_queue_delayed_work(dev->hw, &dev->cal_work,  in mt7601u_phy_set_channel()
469 	if (dev->freq_cal.enabled)  in mt7601u_phy_set_channel()
470 		ieee80211_queue_delayed_work(dev->hw, &dev->freq_cal.work,  in mt7601u_phy_set_channel()
492 static u8 mt7601u_bbp_r47_get(struct mt7601u_dev *dev, u8 reg, u8 flag)  in mt7601u_bbp_r47_get()  argument
495 	mt7601u_bbp_wr(dev, 47, flag);  in mt7601u_bbp_r47_get()
497 	return mt7601u_bbp_rr(dev, 49);  in mt7601u_bbp_r47_get()
500 static s8 mt7601u_read_bootup_temp(struct mt7601u_dev *dev)  in mt7601u_read_bootup_temp()  argument
506 	rf_set = mt7601u_rr(dev, MT_RF_SETTING_0);  in mt7601u_read_bootup_temp()
507 	rf_bp = mt7601u_rr(dev, MT_RF_BYPASS_0);  in mt7601u_read_bootup_temp()
509 	mt7601u_wr(dev, MT_RF_BYPASS_0, 0);  in mt7601u_read_bootup_temp()
510 	mt7601u_wr(dev, MT_RF_SETTING_0, 0x00000010);  in mt7601u_read_bootup_temp()
511 	mt7601u_wr(dev, MT_RF_BYPASS_0, 0x00000010);  in mt7601u_read_bootup_temp()
513 	bbp_val = mt7601u_bbp_rmw(dev, 47, 0, 0x10);  in mt7601u_read_bootup_temp()
515 	mt7601u_bbp_wr(dev, 22, 0x40);  in mt7601u_read_bootup_temp()
518 		bbp_val = mt7601u_bbp_rr(dev, 47);  in mt7601u_read_bootup_temp()
520 	temp = mt7601u_bbp_r47_get(dev, bbp_val, BBP_R47_F_TEMP);  in mt7601u_read_bootup_temp()
522 	mt7601u_bbp_wr(dev, 22, 0);  in mt7601u_read_bootup_temp()
524 	bbp_val = mt7601u_bbp_rr(dev, 21);  in mt7601u_read_bootup_temp()
526 	mt7601u_bbp_wr(dev, 21, bbp_val);  in mt7601u_read_bootup_temp()
528 	mt7601u_bbp_wr(dev, 21, bbp_val);  in mt7601u_read_bootup_temp()
530 	mt7601u_wr(dev, MT_RF_BYPASS_0, 0);  in mt7601u_read_bootup_temp()
531 	mt7601u_wr(dev, MT_RF_SETTING_0, rf_set);  in mt7601u_read_bootup_temp()
532 	mt7601u_wr(dev, MT_RF_BYPASS_0, rf_bp);  in mt7601u_read_bootup_temp()
534 	trace_read_temp(dev, temp);  in mt7601u_read_bootup_temp()
538 static s8 mt7601u_read_temp(struct mt7601u_dev *dev)  in mt7601u_read_temp()  argument
544 	val = mt7601u_bbp_rmw(dev, 47, 0x7f, 0x10);  in mt7601u_read_temp()
548 		val = mt7601u_bbp_rr(dev, 47);  in mt7601u_read_temp()
550 	temp = mt7601u_bbp_r47_get(dev, val, BBP_R47_F_TEMP);  in mt7601u_read_temp()
552 	trace_read_temp(dev, temp);  in mt7601u_read_temp()
556 static void mt7601u_rxdc_cal(struct mt7601u_dev *dev)  in mt7601u_rxdc_cal()  argument
567 	mac_ctrl = mt7601u_rr(dev, MT_MAC_SYS_CTRL);  in mt7601u_rxdc_cal()
568 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX);  in mt7601u_rxdc_cal()
570 	ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP,  in mt7601u_rxdc_cal()
573 		dev_err(dev->dev, "%s intro failed:%d\n", __func__, ret);  in mt7601u_rxdc_cal()
578 		mt7601u_bbp_wr(dev, 158, 0x8c);  in mt7601u_rxdc_cal()
579 		if (mt7601u_bbp_rr(dev, 159) == 0x0c)  in mt7601u_rxdc_cal()
583 		dev_err(dev->dev, "%s timed out\n", __func__);  in mt7601u_rxdc_cal()
585 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0);  in mt7601u_rxdc_cal()
587 	ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP,  in mt7601u_rxdc_cal()
590 		dev_err(dev->dev, "%s outro failed:%d\n", __func__, ret);  in mt7601u_rxdc_cal()
592 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, mac_ctrl);  in mt7601u_rxdc_cal()
595 void mt7601u_phy_recalibrate_after_assoc(struct mt7601u_dev *dev)  in mt7601u_phy_recalibrate_after_assoc()  argument
597 	mt7601u_mcu_calibrate(dev, MCU_CAL_DPD, dev->curr_temp);  in mt7601u_phy_recalibrate_after_assoc()
599 	mt7601u_rxdc_cal(dev);  in mt7601u_phy_recalibrate_after_assoc()
635 mt7601u_set_initial_tssi(struct mt7601u_dev *dev, s16 tssi_db, s16 tssi_hvga_db)  in mt7601u_set_initial_tssi()  argument
637 	struct tssi_data *d = &dev->ee->tssi_data;  in mt7601u_set_initial_tssi()
642 	mt76_rmw(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP,  in mt7601u_set_initial_tssi()
646 static void mt7601u_tssi_dc_gain_cal(struct mt7601u_dev *dev)  in mt7601u_tssi_dc_gain_cal()  argument
653 	mt7601u_wr(dev, MT_RF_SETTING_0, 0x00000030);  in mt7601u_tssi_dc_gain_cal()
654 	mt7601u_wr(dev, MT_RF_BYPASS_0, 0x000c0030);  in mt7601u_tssi_dc_gain_cal()
655 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0);  in mt7601u_tssi_dc_gain_cal()
657 	mt7601u_bbp_wr(dev, 58, 0);  in mt7601u_tssi_dc_gain_cal()
658 	mt7601u_bbp_wr(dev, 241, 0x2);  in mt7601u_tssi_dc_gain_cal()
659 	mt7601u_bbp_wr(dev, 23, 0x8);  in mt7601u_tssi_dc_gain_cal()
660 	bbp_r47 = mt7601u_bbp_rr(dev, 47);  in mt7601u_tssi_dc_gain_cal()
663 	rf_vga = mt7601u_rf_rr(dev, 5, 3);  in mt7601u_tssi_dc_gain_cal()
664 	mt7601u_rf_wr(dev, 5, 3, 8);  in mt7601u_tssi_dc_gain_cal()
667 	rf_mixer = mt7601u_rf_rr(dev, 4, 39);  in mt7601u_tssi_dc_gain_cal()
668 	mt7601u_rf_wr(dev, 4, 39, 0);  in mt7601u_tssi_dc_gain_cal()
671 		mt7601u_rf_wr(dev, 4, 39, (i & 1) ? rf_mixer : 0);  in mt7601u_tssi_dc_gain_cal()
673 		mt7601u_bbp_wr(dev, 23, (i < 2) ? 0x08 : 0x02);  in mt7601u_tssi_dc_gain_cal()
674 		mt7601u_rf_wr(dev, 5, 3, (i < 2) ? 0x08 : 0x11);  in mt7601u_tssi_dc_gain_cal()
677 		mt7601u_bbp_wr(dev, 22, 0);  in mt7601u_tssi_dc_gain_cal()
678 		mt7601u_bbp_wr(dev, 244, 0);  in mt7601u_tssi_dc_gain_cal()
680 		mt7601u_bbp_wr(dev, 21, 1);  in mt7601u_tssi_dc_gain_cal()
682 		mt7601u_bbp_wr(dev, 21, 0);  in mt7601u_tssi_dc_gain_cal()
685 		mt7601u_bbp_wr(dev, 47, 0x50);  in mt7601u_tssi_dc_gain_cal()
686 		mt7601u_bbp_wr(dev, (i & 1) ? 244 : 22, (i & 1) ? 0x31 : 0x40);  in mt7601u_tssi_dc_gain_cal()
689 			if (!(mt7601u_bbp_rr(dev, 47) & 0x10))  in mt7601u_tssi_dc_gain_cal()
692 			dev_err(dev->dev, "%s timed out\n", __func__);  in mt7601u_tssi_dc_gain_cal()
695 		mt7601u_bbp_wr(dev, 47, 0x40);  in mt7601u_tssi_dc_gain_cal()
696 		res[i] = mt7601u_bbp_rr(dev, 49);  in mt7601u_tssi_dc_gain_cal()
701 	dev->tssi_init = res[0];  in mt7601u_tssi_dc_gain_cal()
702 	dev->tssi_init_hvga = res[2];  in mt7601u_tssi_dc_gain_cal()
703 	dev->tssi_init_hvga_offset_db = tssi_init_hvga_db - tssi_init_db;  in mt7601u_tssi_dc_gain_cal()
705 	dev_dbg(dev->dev,  in mt7601u_tssi_dc_gain_cal()
707 		dev->tssi_init, tssi_init_db, dev->tssi_init_hvga,  in mt7601u_tssi_dc_gain_cal()
708 		tssi_init_hvga_db, dev->tssi_init_hvga_offset_db);  in mt7601u_tssi_dc_gain_cal()
710 	mt7601u_bbp_wr(dev, 22, 0);  in mt7601u_tssi_dc_gain_cal()
711 	mt7601u_bbp_wr(dev, 244, 0);  in mt7601u_tssi_dc_gain_cal()
713 	mt7601u_bbp_wr(dev, 21, 1);  in mt7601u_tssi_dc_gain_cal()
715 	mt7601u_bbp_wr(dev, 21, 0);  in mt7601u_tssi_dc_gain_cal()
717 	mt7601u_wr(dev, MT_RF_BYPASS_0, 0);  in mt7601u_tssi_dc_gain_cal()
718 	mt7601u_wr(dev, MT_RF_SETTING_0, 0);  in mt7601u_tssi_dc_gain_cal()
720 	mt7601u_rf_wr(dev, 5, 3, rf_vga);  in mt7601u_tssi_dc_gain_cal()
721 	mt7601u_rf_wr(dev, 4, 39, rf_mixer);  in mt7601u_tssi_dc_gain_cal()
722 	mt7601u_bbp_wr(dev, 47, bbp_r47);  in mt7601u_tssi_dc_gain_cal()
724 	mt7601u_set_initial_tssi(dev, tssi_init_db, tssi_init_hvga_db);  in mt7601u_tssi_dc_gain_cal()
727 static int mt7601u_temp_comp(struct mt7601u_dev *dev, bool on)  in mt7601u_temp_comp()  argument
731 	temp = (dev->raw_temp - dev->ee->ref_temp) * MT_EE_TEMPERATURE_SLOPE;  in mt7601u_temp_comp()
732 	dev->curr_temp = temp;  in mt7601u_temp_comp()
735 	if (temp - dev->dpd_temp > 450 || temp - dev->dpd_temp < -450) {  in mt7601u_temp_comp()
736 		dev->dpd_temp = temp;  in mt7601u_temp_comp()
738 		ret = mt7601u_mcu_calibrate(dev, MCU_CAL_DPD, dev->dpd_temp);  in mt7601u_temp_comp()
742 		mt7601u_vco_cal(dev);  in mt7601u_temp_comp()
744 		dev_dbg(dev->dev, "Recalibrate DPD\n");  in mt7601u_temp_comp()
748 	if (temp < -50 && !dev->pll_lock_protect) { /* < 20C */  in mt7601u_temp_comp()
749 		dev->pll_lock_protect =  true;  in mt7601u_temp_comp()
751 		mt7601u_rf_wr(dev, 4, 4, 6);  in mt7601u_temp_comp()
752 		mt7601u_rf_clear(dev, 4, 10, 0x30);  in mt7601u_temp_comp()
754 		dev_dbg(dev->dev, "PLL lock protect on - too cold\n");  in mt7601u_temp_comp()
755 	} else if (temp > 50 && dev->pll_lock_protect) { /* > 30C */  in mt7601u_temp_comp()
756 		dev->pll_lock_protect = false;  in mt7601u_temp_comp()
758 		mt7601u_rf_wr(dev, 4, 4, 0);  in mt7601u_temp_comp()
759 		mt7601u_rf_rmw(dev, 4, 10, 0x30, 0x10);  in mt7601u_temp_comp()
761 		dev_dbg(dev->dev, "PLL lock protect off\n");  in mt7601u_temp_comp()
771 		return mt7601u_bbp_temp(dev, MT_TEMP_MODE_HIGH, "high");  in mt7601u_temp_comp()
773 		return mt7601u_bbp_temp(dev, MT_TEMP_MODE_NORMAL, "normal");  in mt7601u_temp_comp()
775 		return mt7601u_bbp_temp(dev, MT_TEMP_MODE_LOW, "low");  in mt7601u_temp_comp()
779 static int mt7601u_current_tx_power(struct mt7601u_dev *dev)  in mt7601u_current_tx_power()  argument
781 	return dev->ee->chan_pwr[dev->chandef.chan->hw_value - 1];  in mt7601u_current_tx_power()
784 static bool mt7601u_use_hvga(struct mt7601u_dev *dev)  in mt7601u_use_hvga()  argument
786 	return !(mt7601u_current_tx_power(dev) > 20);  in mt7601u_use_hvga()
790 mt7601u_phy_rf_pa_mode_val(struct mt7601u_dev *dev, int phy_mode, int tx_rate)  in mt7601u_phy_rf_pa_mode_val()  argument
800 		reg = dev->rf_pa_mode[0];  in mt7601u_phy_rf_pa_mode_val()
803 		reg = dev->rf_pa_mode[1];  in mt7601u_phy_rf_pa_mode_val()
811 mt7601u_tssi_params_get(struct mt7601u_dev *dev)  in mt7601u_tssi_params_get()  argument
819 	bbp_r47 = mt7601u_bbp_rr(dev, 47);  in mt7601u_tssi_params_get()
821 	p.tssi0 = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_TSSI);  in mt7601u_tssi_params_get()
822 	dev->raw_temp = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_TEMP);  in mt7601u_tssi_params_get()
823 	pkt_type = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_PKT_T);  in mt7601u_tssi_params_get()
825 	p.trgt_power = mt7601u_current_tx_power(dev);  in mt7601u_tssi_params_get()
830 		rate_table = dev->ee->power_rate_table.cck;  in mt7601u_tssi_params_get()
835 		rate_table = dev->ee->power_rate_table.ofdm;  in mt7601u_tssi_params_get()
839 		tx_rate = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_TX_RATE);  in mt7601u_tssi_params_get()
841 		rate_table = dev->ee->power_rate_table.ht;  in mt7601u_tssi_params_get()
845 	if (dev->bw == MT_BW_20)  in mt7601u_tssi_params_get()
852 	dev_dbg(dev->dev, "tx_rate:%02hhx pwr:%08x\n", tx_rate, p.trgt_power);  in mt7601u_tssi_params_get()
854 	p.trgt_power += mt7601u_phy_rf_pa_mode_val(dev, pkt_type & 0x03,  in mt7601u_tssi_params_get()
859 		if (mt7601u_bbp_rr(dev, 4) & 0x20)  in mt7601u_tssi_params_get()
860 			p.trgt_power += mt7601u_bbp_rr(dev, 178) ? 18022 : 9830;  in mt7601u_tssi_params_get()
862 			p.trgt_power += mt7601u_bbp_rr(dev, 178) ? 819 : 24576;  in mt7601u_tssi_params_get()
865 	p.trgt_power += static_power[mt7601u_bbp_rr(dev, 1) & 0x03];  in mt7601u_tssi_params_get()
867 	p.trgt_power += dev->ee->tssi_data.tx0_delta_offset;  in mt7601u_tssi_params_get()
869 	dev_dbg(dev->dev,  in mt7601u_tssi_params_get()
871 		p.tssi0, p.trgt_power, dev->raw_temp, pkt_type);  in mt7601u_tssi_params_get()
876 static bool mt7601u_tssi_read_ready(struct mt7601u_dev *dev)  in mt7601u_tssi_read_ready()  argument
878 	return !(mt7601u_bbp_rr(dev, 47) & 0x10);  in mt7601u_tssi_read_ready()
881 static int mt7601u_tssi_cal(struct mt7601u_dev *dev)  in mt7601u_tssi_cal()  argument
891 	if (!dev->ee->tssi_enabled)  in mt7601u_tssi_cal()
894 	hvga = mt7601u_use_hvga(dev);  in mt7601u_tssi_cal()
895 	if (!dev->tssi_read_trig)  in mt7601u_tssi_cal()
896 		return mt7601u_mcu_tssi_read_kick(dev, hvga);  in mt7601u_tssi_cal()
898 	if (!mt7601u_tssi_read_ready(dev))  in mt7601u_tssi_cal()
901 	params = mt7601u_tssi_params_get(dev);  in mt7601u_tssi_cal()
903 	tssi_init = (hvga ? dev->tssi_init_hvga : dev->tssi_init);  in mt7601u_tssi_cal()
906 	dev_dbg(dev->dev, "tssi dc:%04hx db:%04hx hvga:%d\n",  in mt7601u_tssi_cal()
909 	if (dev->chandef.chan->hw_value < 5)  in mt7601u_tssi_cal()
910 		tssi_offset = dev->ee->tssi_data.offset[0];  in mt7601u_tssi_cal()
911 	else if (dev->chandef.chan->hw_value < 9)  in mt7601u_tssi_cal()
912 		tssi_offset = dev->ee->tssi_data.offset[1];  in mt7601u_tssi_cal()
914 		tssi_offset = dev->ee->tssi_data.offset[2];  in mt7601u_tssi_cal()
917 		tssi_db -= dev->tssi_init_hvga_offset_db;  in mt7601u_tssi_cal()
919 	curr_pwr = tssi_db * dev->ee->tssi_data.slope + (tssi_offset << 9);  in mt7601u_tssi_cal()
921 	dev_dbg(dev->dev, "Power curr:%08x diff:%08x\n", curr_pwr, diff_pwr);  in mt7601u_tssi_cal()
924 		dev_err(dev->dev, "Error: TSSI upper saturation\n");  in mt7601u_tssi_cal()
928 		dev_err(dev->dev, "Error: TSSI lower saturation\n");  in mt7601u_tssi_cal()
932 	if ((dev->prev_pwr_diff ^ diff_pwr) < 0 && abs(diff_pwr) < 4096 &&  in mt7601u_tssi_cal()
933 	    (abs(diff_pwr) > abs(dev->prev_pwr_diff) ||  in mt7601u_tssi_cal()
934 	     (diff_pwr > 0 && diff_pwr == -dev->prev_pwr_diff)))  in mt7601u_tssi_cal()
937 		dev->prev_pwr_diff = diff_pwr;  in mt7601u_tssi_cal()
942 	dev_dbg(dev->dev, "final diff: %08x\n", diff_pwr);  in mt7601u_tssi_cal()
944 	val = mt7601u_rr(dev, MT_TX_ALC_CFG_1);  in mt7601u_tssi_cal()
948 	mt7601u_wr(dev, MT_TX_ALC_CFG_1, val);  in mt7601u_tssi_cal()
950 	return mt7601u_mcu_tssi_read_kick(dev, hvga);  in mt7601u_tssi_cal()
953 static u8 mt7601u_agc_default(struct mt7601u_dev *dev)  in mt7601u_agc_default()  argument
955 	return (dev->ee->lna_gain - 8) * 2 + 0x34;  in mt7601u_agc_default()
958 static void mt7601u_agc_reset(struct mt7601u_dev *dev)  in mt7601u_agc_reset()  argument
960 	u8 agc = mt7601u_agc_default(dev);  in mt7601u_agc_reset()
962 	mt7601u_bbp_wr(dev, 66,	agc);  in mt7601u_agc_reset()
965 void mt7601u_agc_save(struct mt7601u_dev *dev)  in mt7601u_agc_save()  argument
967 	dev->agc_save = mt7601u_bbp_rr(dev, 66);  in mt7601u_agc_save()
970 void mt7601u_agc_restore(struct mt7601u_dev *dev)  in mt7601u_agc_restore()  argument
972 	mt7601u_bbp_wr(dev, 66, dev->agc_save);  in mt7601u_agc_restore()
975 static void mt7601u_agc_tune(struct mt7601u_dev *dev)  in mt7601u_agc_tune()  argument
977 	u8 val = mt7601u_agc_default(dev);  in mt7601u_agc_tune()
980 	if (test_bit(MT7601U_STATE_SCANNING, &dev->state))  in mt7601u_agc_tune()
987 	spin_lock_bh(&dev->con_mon_lock);  in mt7601u_agc_tune()
988 	avg_rssi = ewma_rssi_read(&dev->avg_rssi);  in mt7601u_agc_tune()
989 	spin_unlock_bh(&dev->con_mon_lock);  in mt7601u_agc_tune()
999 	if (val != mt7601u_bbp_rr(dev, 66))  in mt7601u_agc_tune()
1000 		mt7601u_bbp_wr(dev, 66, val);  in mt7601u_agc_tune()
1009 	struct mt7601u_dev *dev = container_of(work, struct mt7601u_dev,  in mt7601u_phy_calibrate()  local
1012 	mt7601u_agc_tune(dev);  in mt7601u_phy_calibrate()
1013 	mt7601u_tssi_cal(dev);  in mt7601u_phy_calibrate()
1015 	if (!dev->ee->tssi_enabled)  in mt7601u_phy_calibrate()
1016 		dev->raw_temp = mt7601u_read_temp(dev);  in mt7601u_phy_calibrate()
1017 	mt7601u_temp_comp(dev, true); /* TODO: find right value for @on */  in mt7601u_phy_calibrate()
1019 	ieee80211_queue_delayed_work(dev->hw, &dev->cal_work,  in mt7601u_phy_calibrate()
1024 __mt7601u_phy_freq_cal(struct mt7601u_dev *dev, s8 last_offset, u8 phy_mode)  in __mt7601u_phy_freq_cal()  argument
1028 	trace_freq_cal_offset(dev, phy_mode, last_offset);  in __mt7601u_phy_freq_cal()
1054 		dev->freq_cal.adjusting = true;  in __mt7601u_phy_freq_cal()
1056 		dev->freq_cal.adjusting = false;  in __mt7601u_phy_freq_cal()
1058 	if (!dev->freq_cal.adjusting)  in __mt7601u_phy_freq_cal()
1062 		if (dev->freq_cal.freq > 0)  in __mt7601u_phy_freq_cal()
1063 			dev->freq_cal.freq--;  in __mt7601u_phy_freq_cal()
1065 			dev->freq_cal.adjusting = false;  in __mt7601u_phy_freq_cal()
1067 		if (dev->freq_cal.freq < 0xbf)  in __mt7601u_phy_freq_cal()
1068 			dev->freq_cal.freq++;  in __mt7601u_phy_freq_cal()
1070 			dev->freq_cal.adjusting = false;  in __mt7601u_phy_freq_cal()
1073 	trace_freq_cal_adjust(dev, dev->freq_cal.freq);  in __mt7601u_phy_freq_cal()
1074 	mt7601u_rf_wr(dev, 0, 12, dev->freq_cal.freq);  in __mt7601u_phy_freq_cal()
1075 	mt7601u_vco_cal(dev);  in __mt7601u_phy_freq_cal()
1077 	return dev->freq_cal.adjusting ? MT_FREQ_CAL_ADJ_INTERVAL :  in __mt7601u_phy_freq_cal()
1083 	struct mt7601u_dev *dev = container_of(work, struct mt7601u_dev,  in mt7601u_phy_freq_cal()  local
1089 	spin_lock_bh(&dev->con_mon_lock);  in mt7601u_phy_freq_cal()
1090 	last_offset = dev->bcn_freq_off;  in mt7601u_phy_freq_cal()
1091 	phy_mode = dev->bcn_phy_mode;  in mt7601u_phy_freq_cal()
1092 	spin_unlock_bh(&dev->con_mon_lock);  in mt7601u_phy_freq_cal()
1094 	delay = __mt7601u_phy_freq_cal(dev, last_offset, phy_mode);  in mt7601u_phy_freq_cal()
1095 	ieee80211_queue_delayed_work(dev->hw, &dev->freq_cal.work, delay);  in mt7601u_phy_freq_cal()
1097 	spin_lock_bh(&dev->con_mon_lock);  in mt7601u_phy_freq_cal()
1098 	dev->bcn_freq_off = MT_FREQ_OFFSET_INVALID;  in mt7601u_phy_freq_cal()
1099 	spin_unlock_bh(&dev->con_mon_lock);  in mt7601u_phy_freq_cal()
1102 void mt7601u_phy_con_cal_onoff(struct mt7601u_dev *dev,  in mt7601u_phy_con_cal_onoff()  argument
1106 		cancel_delayed_work_sync(&dev->freq_cal.work);  in mt7601u_phy_con_cal_onoff()
1109 	spin_lock_bh(&dev->con_mon_lock);  in mt7601u_phy_con_cal_onoff()
1110 	ether_addr_copy(dev->ap_bssid, info->bssid);  in mt7601u_phy_con_cal_onoff()
1111 	ewma_rssi_init(&dev->avg_rssi);  in mt7601u_phy_con_cal_onoff()
1112 	dev->bcn_freq_off = MT_FREQ_OFFSET_INVALID;  in mt7601u_phy_con_cal_onoff()
1113 	spin_unlock_bh(&dev->con_mon_lock);  in mt7601u_phy_con_cal_onoff()
1115 	dev->freq_cal.freq = dev->ee->rf_freq_off;  in mt7601u_phy_con_cal_onoff()
1116 	dev->freq_cal.enabled = info->assoc;  in mt7601u_phy_con_cal_onoff()
1117 	dev->freq_cal.adjusting = false;  in mt7601u_phy_con_cal_onoff()
1120 		ieee80211_queue_delayed_work(dev->hw, &dev->freq_cal.work,  in mt7601u_phy_con_cal_onoff()
1124 static int mt7601u_init_cal(struct mt7601u_dev *dev)  in mt7601u_init_cal()  argument
1129 	dev->raw_temp = mt7601u_read_bootup_temp(dev);  in mt7601u_init_cal()
1130 	dev->curr_temp = (dev->raw_temp - dev->ee->ref_temp) *  in mt7601u_init_cal()
1132 	dev->dpd_temp = dev->curr_temp;  in mt7601u_init_cal()
1134 	mac_ctrl = mt7601u_rr(dev, MT_MAC_SYS_CTRL);  in mt7601u_init_cal()
1136 	ret = mt7601u_mcu_calibrate(dev, MCU_CAL_R, 0);  in mt7601u_init_cal()
1140 	ret = mt7601u_rf_rr(dev, 0, 4);  in mt7601u_init_cal()
1144 	ret = mt7601u_rf_wr(dev, 0, 4, ret);  in mt7601u_init_cal()
1149 	ret = mt7601u_mcu_calibrate(dev, MCU_CAL_TXDCOC, 0);  in mt7601u_init_cal()
1153 	mt7601u_rxdc_cal(dev);  in mt7601u_init_cal()
1155 	ret = mt7601u_set_bw_filter(dev, true);  in mt7601u_init_cal()
1158 	ret = mt7601u_mcu_calibrate(dev, MCU_CAL_LOFT, 0);  in mt7601u_init_cal()
1161 	ret = mt7601u_mcu_calibrate(dev, MCU_CAL_TXIQ, 0);  in mt7601u_init_cal()
1164 	ret = mt7601u_mcu_calibrate(dev, MCU_CAL_RXIQ, 0);  in mt7601u_init_cal()
1167 	ret = mt7601u_mcu_calibrate(dev, MCU_CAL_DPD, dev->dpd_temp);  in mt7601u_init_cal()
1171 	mt7601u_rxdc_cal(dev);  in mt7601u_init_cal()
1173 	mt7601u_tssi_dc_gain_cal(dev);  in mt7601u_init_cal()
1175 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, mac_ctrl);  in mt7601u_init_cal()
1177 	mt7601u_temp_comp(dev, true);  in mt7601u_init_cal()
1182 int mt7601u_bbp_set_bw(struct mt7601u_dev *dev, int bw)  in mt7601u_bbp_set_bw()  argument
1186 	if (bw == dev->bw) {  in mt7601u_bbp_set_bw()
1188 		mt7601u_bbp_rmc(dev, 4, 0x18, bw == MT_BW_20 ? 0 : 0x10);  in mt7601u_bbp_set_bw()
1192 	dev->bw = bw;  in mt7601u_bbp_set_bw()
1195 	old = mt7601u_rr(dev, MT_MAC_SYS_CTRL);  in mt7601u_bbp_set_bw()
1197 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, val);  in mt7601u_bbp_set_bw()
1198 	mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_TX | MT_MAC_STATUS_RX,  in mt7601u_bbp_set_bw()
1201 	mt7601u_bbp_rmc(dev, 4, 0x18, bw == MT_BW_20 ? 0 : 0x10);  in mt7601u_bbp_set_bw()
1203 	mt7601u_wr(dev, MT_MAC_SYS_CTRL, old);  in mt7601u_bbp_set_bw()
1205 	return mt7601u_load_bbp_temp_table_bw(dev);  in mt7601u_bbp_set_bw()
1213 void mt7601u_set_rx_path(struct mt7601u_dev *dev, u8 path)  in mt7601u_set_rx_path()  argument
1215 	mt7601u_bbp_rmw(dev, 3, 0x18, path << 3);  in mt7601u_set_rx_path()
1223 void mt7601u_set_tx_dac(struct mt7601u_dev *dev, u8 dac)  in mt7601u_set_tx_dac()  argument
1225 	mt7601u_bbp_rmc(dev, 1, 0x18, dac << 3);  in mt7601u_set_tx_dac()
1228 int mt7601u_phy_init(struct mt7601u_dev *dev)  in mt7601u_phy_init()  argument
1232 	dev->rf_pa_mode[0] = mt7601u_rr(dev, MT_RF_PA_MODE_CFG0);  in mt7601u_phy_init()
1233 	dev->rf_pa_mode[1] = mt7601u_rr(dev, MT_RF_PA_MODE_CFG1);  in mt7601u_phy_init()
1235 	ret = mt7601u_rf_wr(dev, 0, 12, dev->ee->rf_freq_off);  in mt7601u_phy_init()
1238 	ret = mt7601u_write_reg_pairs(dev, 0, rf_central,  in mt7601u_phy_init()
1242 	ret = mt7601u_write_reg_pairs(dev, 0, rf_channel,  in mt7601u_phy_init()
1246 	ret = mt7601u_write_reg_pairs(dev, 0, rf_vga, ARRAY_SIZE(rf_vga));  in mt7601u_phy_init()
1250 	ret = mt7601u_init_cal(dev);  in mt7601u_phy_init()
1254 	dev->prev_pwr_diff = 100;  in mt7601u_phy_init()
1256 	INIT_DELAYED_WORK(&dev->cal_work, mt7601u_phy_calibrate);  in mt7601u_phy_init()
1257 	INIT_DELAYED_WORK(&dev->freq_cal.work, mt7601u_phy_freq_cal);  in mt7601u_phy_init()