57 	mt76_wr(dev, 0x504, 0x06000000);  in mt76x2u_mac_fixup_xtal()
58 	mt76_wr(dev, 0x50c, 0x08800000);  in mt76x2u_mac_fixup_xtal()
60 	mt76_wr(dev, 0x504, 0x0);  in mt76x2u_mac_fixup_xtal()
73 		mt76_wr(dev, MT_XO_CTRL7, 0x5c1fee80);  in mt76x2u_mac_fixup_xtal()
76 		mt76_wr(dev, MT_XO_CTRL7, 0x5c1feed0);  in mt76x2u_mac_fixup_xtal()
85 	mt76_wr(dev, MT_WPDMA_GLO_CFG, BIT(4) | BIT(5));  in mt76x2u_mac_reset()
88 	mt76_wr(dev, MT_PBF_TX_MAX_PCNT, 0xefef3f1f);  in mt76x2u_mac_reset()
89 	mt76_wr(dev, MT_PBF_RX_MAX_PCNT, 0xfebf);  in mt76x2u_mac_reset()
93 	mt76_wr(dev, MT_TX_LINK_CFG, 0x1020);  in mt76x2u_mac_reset()
94 	mt76_wr(dev, MT_AUTO_RSP_CFG, 0x13);  in mt76x2u_mac_reset()
95 	mt76_wr(dev, MT_MAX_LEN_CFG, 0x2f00);  in mt76x2u_mac_reset()
96 	mt76_wr(dev, MT_TX_RTS_CFG, 0x92b20);  in mt76x2u_mac_reset()
98 	mt76_wr(dev, MT_WMM_AIFSN, 0x2273);  in mt76x2u_mac_reset()
99 	mt76_wr(dev, MT_WMM_CWMIN, 0x2344);  in mt76x2u_mac_reset()
100 	mt76_wr(dev, MT_WMM_CWMAX, 0x34aa);  in mt76x2u_mac_reset()
121 	mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);  in mt76x2u_mac_start()
125 	mt76_wr(dev, MT_RX_FILTR_CFG, dev->rxfilter);  in mt76x2u_mac_start()
127 	mt76_wr(dev, MT_MAC_SYS_CTRL,  in mt76x2u_mac_start()
144 	mt76_wr(dev, MT_TX_RTS_CFG, rts_cfg & ~MT_TX_RTS_CFG_RETRY_LIMIT);  in mt76x2u_mac_stop()
210 	mt76_wr(dev, MT_TX_RTS_CFG, rts_cfg);  in mt76x2u_mac_stop()
217 	mt76_wr(dev, MT_MAC_SYS_CTRL,  in mt76x2u_mac_resume()
235 	mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(dev->mt76.macaddr));  in mt76x2u_mac_setaddr()
236 	mt76_wr(dev, MT_MAC_ADDR_DW1,  in mt76x2u_mac_setaddr()