85 	if (q->n_window < trans->cfg->base_params->max_tfd_queue_size)  in iwl_queue_space()
88 		max = trans->cfg->base_params->max_tfd_queue_size - 1;  in iwl_queue_space()
95 		(trans->cfg->base_params->max_tfd_queue_size - 1);  in iwl_queue_space()
264 	if (!trans->cfg->base_params->shadow_reg_enable &&  in iwl_pcie_txq_inc_wr_ptr()
299 	for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {  in iwl_pcie_txq_check_wrptrs()
494 		trans->cfg->base_params->max_tfd_queue_size;  in iwl_pcie_txq_alloc()
560 	u32 tfd_queue_max_size = trans->cfg->base_params->max_tfd_queue_size;  in iwl_pcie_txq_init()
614 	if (!trans->cfg->base_params->apmg_wake_up_wa)  in iwl_pcie_clear_cmd_in_flight()
706 				  trans->cfg->base_params->max_tfd_queue_size,  in iwl_pcie_txq_free()
728 	int nq = trans->cfg->base_params->num_of_queues;  in iwl_pcie_tx_start()
755 	if (trans->cfg->base_params->scd_chain_ext_wa)  in iwl_pcie_tx_start()
794 	for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;  in iwl_trans_pcie_tx_reset()
880 	for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;  in iwl_pcie_tx_stop()
902 		     txq_id < trans->cfg->base_params->num_of_queues;  in iwl_pcie_tx_free()
926 	u16 bc_tbls_size = trans->cfg->base_params->num_of_queues;  in iwl_pcie_tx_alloc()
953 	trans_pcie->txq_memory = kcalloc(trans->cfg->base_params->num_of_queues,  in iwl_pcie_tx_alloc()
962 	for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;  in iwl_pcie_tx_alloc()
1011 	for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;  in iwl_pcie_tx_init()
1034 	if (trans->cfg->base_params->num_of_queues > 20)  in iwl_pcie_tx_init()
1106 			trans->cfg->base_params->max_tfd_queue_size,  in iwl_trans_pcie_reclaim()
1204 	if (cfg->base_params->apmg_wake_up_wa &&  in iwl_pcie_set_cmd_in_flight()
1246 	if (idx >= trans->cfg->base_params->max_tfd_queue_size ||  in iwl_pcie_cmdq_reclaim()
1251 			trans->cfg->base_params->max_tfd_queue_size,  in iwl_pcie_cmdq_reclaim()