414 	struct iwl_trans_pcie *trans_pcie;  member
658 iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie)  in iwl_trans_pcie_get_trans()  argument
660 	return container_of((void *)trans_pcie, struct iwl_trans,  in iwl_trans_pcie_get_trans()
752 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);  in _iwl_disable_interrupts()  local
755 	if (!trans_pcie->msix_enabled) {  in _iwl_disable_interrupts()
766 			    trans_pcie->fh_init_mask);  in _iwl_disable_interrupts()
768 			    trans_pcie->hw_init_mask);  in _iwl_disable_interrupts()
809 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);  in iwl_pcie_ctxt_info_free_fw_img()  local
810 	struct iwl_self_init_dram *dram = &trans_pcie->init_dram;  in iwl_pcie_ctxt_info_free_fw_img()
829 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);  in iwl_disable_interrupts()  local
831 	spin_lock(&trans_pcie->irq_lock);  in iwl_disable_interrupts()
833 	spin_unlock(&trans_pcie->irq_lock);  in iwl_disable_interrupts()
838 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);  in _iwl_enable_interrupts()  local
842 	if (!trans_pcie->msix_enabled) {  in _iwl_enable_interrupts()
843 		trans_pcie->inta_mask = CSR_INI_SET_MASK;  in _iwl_enable_interrupts()
844 		iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);  in _iwl_enable_interrupts()
850 		trans_pcie->hw_mask = trans_pcie->hw_init_mask;  in _iwl_enable_interrupts()
851 		trans_pcie->fh_mask = trans_pcie->fh_init_mask;  in _iwl_enable_interrupts()
853 			    ~trans_pcie->fh_mask);  in _iwl_enable_interrupts()
855 			    ~trans_pcie->hw_mask);  in _iwl_enable_interrupts()
861 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);  in iwl_enable_interrupts()  local
863 	spin_lock(&trans_pcie->irq_lock);  in iwl_enable_interrupts()
865 	spin_unlock(&trans_pcie->irq_lock);  in iwl_enable_interrupts()
869 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);  in iwl_enable_hw_int_msk_msix()  local
872 	trans_pcie->hw_mask = msk;  in iwl_enable_hw_int_msk_msix()
877 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);  in iwl_enable_fh_int_msk_msix()  local
880 	trans_pcie->fh_mask = msk;  in iwl_enable_fh_int_msk_msix()
885 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);  in iwl_enable_fw_load_int()  local
888 	if (!trans_pcie->msix_enabled) {  in iwl_enable_fw_load_int()
889 		trans_pcie->inta_mask = CSR_INT_BIT_FH_TX;  in iwl_enable_fw_load_int()
890 		iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);  in iwl_enable_fw_load_int()
893 			    trans_pcie->hw_init_mask);  in iwl_enable_fw_load_int()
907 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);  in iwl_pcie_get_tfd()  local
912 	return txq->tfds + trans_pcie->tfd_size * idx;  in iwl_pcie_get_tfd()
940 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);  in iwl_enable_rfkill_int()  local
943 	if (!trans_pcie->msix_enabled) {  in iwl_enable_rfkill_int()
944 		trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL;  in iwl_enable_rfkill_int()
945 		iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);  in iwl_enable_rfkill_int()
948 			    trans_pcie->fh_init_mask);  in iwl_enable_rfkill_int()
969 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);  in iwl_wake_queue()  local
971 	if (test_and_clear_bit(txq->id, trans_pcie->queue_stopped)) {  in iwl_wake_queue()
980 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);  in iwl_stop_queue()  local
982 	if (!test_and_set_bit(txq->id, trans_pcie->queue_stopped)) {  in iwl_stop_queue()
1003 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);  in iwl_is_rfkill_set()  local
1005 	lockdep_assert_held(&trans_pcie->mutex);  in iwl_is_rfkill_set()
1007 	if (trans_pcie->debug_rfkill)  in iwl_is_rfkill_set()
1069 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie);
1078 void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie,