Lines Matching refs:iwl_write32
654 iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(entry->entry)); in iwl_pcie_clear_irq()
757 iwl_write32(trans, CSR_INT_MASK, 0x00000000); in _iwl_disable_interrupts()
761 iwl_write32(trans, CSR_INT, 0xffffffff); in _iwl_disable_interrupts()
762 iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff); in _iwl_disable_interrupts()
765 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, in _iwl_disable_interrupts()
767 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, in _iwl_disable_interrupts()
844 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); in _iwl_enable_interrupts()
852 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, in _iwl_enable_interrupts()
854 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, in _iwl_enable_interrupts()
871 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk); in iwl_enable_hw_int_msk_msix()
879 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk); in iwl_enable_fh_int_msk_msix()
890 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); in iwl_enable_fw_load_int()
892 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, in iwl_enable_fw_load_int()
945 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); in iwl_enable_rfkill_int()
947 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, in iwl_enable_rfkill_int()
1026 iwl_write32(trans, reg, v); in __iwl_trans_pcie_set_bits_mask()