37 	b43_phy_write(dev, B43_PHY_LNAHPFCTL, 0x1FF9);  in b43_wa_initgains()
43 	b43_phy_write(dev, 0x0024, 0x4680);  in b43_wa_initgains()
44 	b43_phy_write(dev, 0x0020, 0x0003);  in b43_wa_initgains()
45 	b43_phy_write(dev, 0x001D, 0x0F40);  in b43_wa_initgains()
46 	b43_phy_write(dev, 0x001F, 0x1C00);  in b43_wa_initgains()
51 		b43_phy_write(dev, 0x00CC, 0x2121);  in b43_wa_initgains()
54 		b43_phy_write(dev, 0x00BA, 0x3ED5);  in b43_wa_initgains()
78 		b43_phy_write(dev, B43_PHY_PWRDOWN, 0x1000);  in b43_wa_analog()
173 		b43_phy_write(dev, B43_PHY_CRSTHRES1_R1, 0x4F19);  in b43_wa_crs_ed()
175 		b43_phy_write(dev, B43_PHY_CRSTHRES1, 0x1861);  in b43_wa_crs_ed()
176 		b43_phy_write(dev, B43_PHY_CRSTHRES2, 0x0271);  in b43_wa_crs_ed()
179 		b43_phy_write(dev, B43_PHY_CRSTHRES1, 0x0098);  in b43_wa_crs_ed()
180 		b43_phy_write(dev, B43_PHY_CRSTHRES2, 0x0070);  in b43_wa_crs_ed()
181 		b43_phy_write(dev, B43_PHY_OFDM(0xC9), 0x0080);  in b43_wa_crs_ed()
193 	b43_phy_write(dev, B43_PHY_OFDM(0x2C), 0x005A);  in b43_wa_crs_blank()
198 	b43_phy_write(dev, B43_PHY_CCKSHIFTBITS, 0x0026);  in b43_wa_cck_shiftbits()
237 		b43_phy_write(dev, B43_PHY_LMS, 4);  in b43_wa_altagc()
267 		b43_phy_write(dev, B43_PHY_PEAK_COUNT, 0x092B);  in b43_wa_altagc()
271 		b43_phy_write(dev, B43_PHY_OFDM(0x1F), 0x287A);  in b43_wa_altagc()
274 			b43_phy_write(dev, B43_PHY_OFDM(0x22), 0x287A);  in b43_wa_altagc()
279 	b43_phy_write(dev, B43_PHY_OFDM(0x8E), 0x1C00);  in b43_wa_altagc()
282 		b43_phy_write(dev, B43_PHY_OFDM(0x8B), 0x005E);  in b43_wa_altagc()
284 		b43_phy_write(dev, B43_PHY_OFDM(0x8D), 0x0002);  in b43_wa_altagc()
340 		b43_phy_write(dev, B43_PHY_GTABCTL, 0x3120);  in b43_wa_boards_g()
341 		b43_phy_write(dev, B43_PHY_GTABDATA, 0xC480);  in b43_wa_boards_g()