Lines Matching refs:dev
67 static void b43_calc_nrssi_threshold(struct b43_wldev *dev);
81 static void generate_rfatt_list(struct b43_wldev *dev, in generate_rfatt_list() argument
84 struct b43_phy *phy = &dev->phy; in generate_rfatt_list()
124 if (!b43_has_hardware_pctl(dev)) { in generate_rfatt_list()
147 static void generate_bbatt_list(struct b43_wldev *dev, in generate_bbatt_list() argument
168 static void b43_shm_clear_tssi(struct b43_wldev *dev) in b43_shm_clear_tssi() argument
170 b43_shm_write16(dev, B43_SHM_SHARED, 0x0058, 0x7F7F); in b43_shm_clear_tssi()
171 b43_shm_write16(dev, B43_SHM_SHARED, 0x005a, 0x7F7F); in b43_shm_clear_tssi()
172 b43_shm_write16(dev, B43_SHM_SHARED, 0x0070, 0x7F7F); in b43_shm_clear_tssi()
173 b43_shm_write16(dev, B43_SHM_SHARED, 0x0072, 0x7F7F); in b43_shm_clear_tssi()
177 static void b43_synth_pu_workaround(struct b43_wldev *dev, u8 channel) in b43_synth_pu_workaround() argument
179 struct b43_phy *phy = &dev->phy; in b43_synth_pu_workaround()
189 b43_write16(dev, B43_MMIO_CHANNEL, in b43_synth_pu_workaround()
192 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(1)); in b43_synth_pu_workaround()
195 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel)); in b43_synth_pu_workaround()
199 void b43_gphy_set_baseband_attenuation(struct b43_wldev *dev, in b43_gphy_set_baseband_attenuation() argument
202 struct b43_phy *phy = &dev->phy; in b43_gphy_set_baseband_attenuation()
205 b43_write16(dev, B43_MMIO_PHY0, (b43_read16(dev, B43_MMIO_PHY0) in b43_gphy_set_baseband_attenuation()
209 b43_phy_maskset(dev, B43_PHY_DACCTL, 0xFFC3, (baseband_attenuation << 2)); in b43_gphy_set_baseband_attenuation()
211 b43_phy_maskset(dev, B43_PHY_DACCTL, 0xFF87, (baseband_attenuation << 3)); in b43_gphy_set_baseband_attenuation()
216 static void b43_set_txpower_g(struct b43_wldev *dev, in b43_set_txpower_g() argument
220 struct b43_phy *phy = &dev->phy; in b43_set_txpower_g()
240 if (b43_debug(dev, B43_DBG_XMITPOWER)) { in b43_set_txpower_g()
241 b43dbg(dev->wl, "Tuning TX-power to bbatt(%u), " in b43_set_txpower_g()
247 b43_gphy_set_baseband_attenuation(dev, bb); in b43_set_txpower_g()
248 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_RFATT, rf); in b43_set_txpower_g()
250 b43_radio_write16(dev, 0x43, in b43_set_txpower_g()
253 b43_radio_maskset(dev, 0x43, 0xFFF0, (rf & 0x000F)); in b43_set_txpower_g()
254 b43_radio_maskset(dev, 0x52, ~0x0070, (tx_control & 0x0070)); in b43_set_txpower_g()
257 b43_radio_write16(dev, 0x52, tx_magn | tx_bias); in b43_set_txpower_g()
259 b43_radio_maskset(dev, 0x52, 0xFFF0, (tx_bias & 0x000F)); in b43_set_txpower_g()
261 b43_lo_g_adjust(dev); in b43_set_txpower_g()
265 static void b43_gphy_tssi_power_lt_init(struct b43_wldev *dev) in b43_gphy_tssi_power_lt_init() argument
267 struct b43_phy_g *gphy = dev->phy.g; in b43_gphy_tssi_power_lt_init()
272 b43_ofdmtab_write16(dev, 0x3C20, i, gphy->tssi2dbm[i]); in b43_gphy_tssi_power_lt_init()
274 b43_ofdmtab_write16(dev, 0x3C00, i - 32, gphy->tssi2dbm[i]); in b43_gphy_tssi_power_lt_init()
278 b43_phy_write(dev, 0x380 + (i / 2), value); in b43_gphy_tssi_power_lt_init()
283 static void b43_gphy_gain_lt_init(struct b43_wldev *dev) in b43_gphy_gain_lt_init() argument
285 struct b43_phy *phy = &dev->phy; in b43_gphy_gain_lt_init()
303 b43_phy_write(dev, 0x3C0 + nr_written, tmp); in b43_gphy_gain_lt_init()
309 static void b43_set_all_gains(struct b43_wldev *dev, in b43_set_all_gains() argument
312 struct b43_phy *phy = &dev->phy; in b43_set_all_gains()
327 b43_ofdmtab_write16(dev, table, i, first); in b43_set_all_gains()
330 b43_ofdmtab_write16(dev, table, i, second); in b43_set_all_gains()
334 b43_phy_maskset(dev, 0x04A0, 0xBFBF, tmp); in b43_set_all_gains()
335 b43_phy_maskset(dev, 0x04A1, 0xBFBF, tmp); in b43_set_all_gains()
336 b43_phy_maskset(dev, 0x04A2, 0xBFBF, tmp); in b43_set_all_gains()
338 b43_dummy_transmission(dev, false, true); in b43_set_all_gains()
341 static void b43_set_original_gains(struct b43_wldev *dev) in b43_set_original_gains() argument
343 struct b43_phy *phy = &dev->phy; in b43_set_original_gains()
361 b43_ofdmtab_write16(dev, table, i, tmp); in b43_set_original_gains()
365 b43_ofdmtab_write16(dev, table, i, i - start); in b43_set_original_gains()
367 b43_phy_maskset(dev, 0x04A0, 0xBFBF, 0x4040); in b43_set_original_gains()
368 b43_phy_maskset(dev, 0x04A1, 0xBFBF, 0x4040); in b43_set_original_gains()
369 b43_phy_maskset(dev, 0x04A2, 0xBFBF, 0x4000); in b43_set_original_gains()
370 b43_dummy_transmission(dev, false, true); in b43_set_original_gains()
374 static void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val) in b43_nrssi_hw_write() argument
376 b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset); in b43_nrssi_hw_write()
377 b43_phy_write(dev, B43_PHY_NRSSILT_DATA, (u16) val); in b43_nrssi_hw_write()
381 static s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset) in b43_nrssi_hw_read() argument
385 b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset); in b43_nrssi_hw_read()
386 val = b43_phy_read(dev, B43_PHY_NRSSILT_DATA); in b43_nrssi_hw_read()
392 static void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val) in b43_nrssi_hw_update() argument
398 tmp = b43_nrssi_hw_read(dev, i); in b43_nrssi_hw_update()
401 b43_nrssi_hw_write(dev, i, tmp); in b43_nrssi_hw_update()
406 static void b43_nrssi_mem_update(struct b43_wldev *dev) in b43_nrssi_mem_update() argument
408 struct b43_phy_g *gphy = dev->phy.g; in b43_nrssi_mem_update()
422 static void b43_calc_nrssi_offset(struct b43_wldev *dev) in b43_calc_nrssi_offset() argument
424 struct b43_phy *phy = &dev->phy; in b43_calc_nrssi_offset()
430 backup[0] = b43_phy_read(dev, 0x0001); in b43_calc_nrssi_offset()
431 backup[1] = b43_phy_read(dev, 0x0811); in b43_calc_nrssi_offset()
432 backup[2] = b43_phy_read(dev, 0x0812); in b43_calc_nrssi_offset()
434 backup[3] = b43_phy_read(dev, 0x0814); in b43_calc_nrssi_offset()
435 backup[4] = b43_phy_read(dev, 0x0815); in b43_calc_nrssi_offset()
437 backup[5] = b43_phy_read(dev, 0x005A); in b43_calc_nrssi_offset()
438 backup[6] = b43_phy_read(dev, 0x0059); in b43_calc_nrssi_offset()
439 backup[7] = b43_phy_read(dev, 0x0058); in b43_calc_nrssi_offset()
440 backup[8] = b43_phy_read(dev, 0x000A); in b43_calc_nrssi_offset()
441 backup[9] = b43_phy_read(dev, 0x0003); in b43_calc_nrssi_offset()
442 backup[10] = b43_radio_read16(dev, 0x007A); in b43_calc_nrssi_offset()
443 backup[11] = b43_radio_read16(dev, 0x0043); in b43_calc_nrssi_offset()
445 b43_phy_mask(dev, 0x0429, 0x7FFF); in b43_calc_nrssi_offset()
446 b43_phy_maskset(dev, 0x0001, 0x3FFF, 0x4000); in b43_calc_nrssi_offset()
447 b43_phy_set(dev, 0x0811, 0x000C); in b43_calc_nrssi_offset()
448 b43_phy_maskset(dev, 0x0812, 0xFFF3, 0x0004); in b43_calc_nrssi_offset()
449 b43_phy_mask(dev, 0x0802, ~(0x1 | 0x2)); in b43_calc_nrssi_offset()
451 backup[12] = b43_phy_read(dev, 0x002E); in b43_calc_nrssi_offset()
452 backup[13] = b43_phy_read(dev, 0x002F); in b43_calc_nrssi_offset()
453 backup[14] = b43_phy_read(dev, 0x080F); in b43_calc_nrssi_offset()
454 backup[15] = b43_phy_read(dev, 0x0810); in b43_calc_nrssi_offset()
455 backup[16] = b43_phy_read(dev, 0x0801); in b43_calc_nrssi_offset()
456 backup[17] = b43_phy_read(dev, 0x0060); in b43_calc_nrssi_offset()
457 backup[18] = b43_phy_read(dev, 0x0014); in b43_calc_nrssi_offset()
458 backup[19] = b43_phy_read(dev, 0x0478); in b43_calc_nrssi_offset()
460 b43_phy_write(dev, 0x002E, 0); in b43_calc_nrssi_offset()
461 b43_phy_write(dev, 0x002F, 0); in b43_calc_nrssi_offset()
462 b43_phy_write(dev, 0x080F, 0); in b43_calc_nrssi_offset()
463 b43_phy_write(dev, 0x0810, 0); in b43_calc_nrssi_offset()
464 b43_phy_set(dev, 0x0478, 0x0100); in b43_calc_nrssi_offset()
465 b43_phy_set(dev, 0x0801, 0x0040); in b43_calc_nrssi_offset()
466 b43_phy_set(dev, 0x0060, 0x0040); in b43_calc_nrssi_offset()
467 b43_phy_set(dev, 0x0014, 0x0200); in b43_calc_nrssi_offset()
469 b43_radio_set(dev, 0x007A, 0x0070); in b43_calc_nrssi_offset()
470 b43_radio_set(dev, 0x007A, 0x0080); in b43_calc_nrssi_offset()
473 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F); in b43_calc_nrssi_offset()
478 b43_radio_write16(dev, 0x007B, i); in b43_calc_nrssi_offset()
481 (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F); in b43_calc_nrssi_offset()
490 b43_radio_mask(dev, 0x007A, 0x007F); in b43_calc_nrssi_offset()
492 b43_phy_set(dev, 0x0814, 0x0001); in b43_calc_nrssi_offset()
493 b43_phy_mask(dev, 0x0815, 0xFFFE); in b43_calc_nrssi_offset()
495 b43_phy_set(dev, 0x0811, 0x000C); in b43_calc_nrssi_offset()
496 b43_phy_set(dev, 0x0812, 0x000C); in b43_calc_nrssi_offset()
497 b43_phy_set(dev, 0x0811, 0x0030); in b43_calc_nrssi_offset()
498 b43_phy_set(dev, 0x0812, 0x0030); in b43_calc_nrssi_offset()
499 b43_phy_write(dev, 0x005A, 0x0480); in b43_calc_nrssi_offset()
500 b43_phy_write(dev, 0x0059, 0x0810); in b43_calc_nrssi_offset()
501 b43_phy_write(dev, 0x0058, 0x000D); in b43_calc_nrssi_offset()
503 b43_phy_write(dev, 0x0003, 0x0122); in b43_calc_nrssi_offset()
505 b43_phy_set(dev, 0x000A, 0x2000); in b43_calc_nrssi_offset()
508 b43_phy_set(dev, 0x0814, 0x0004); in b43_calc_nrssi_offset()
509 b43_phy_mask(dev, 0x0815, 0xFFFB); in b43_calc_nrssi_offset()
511 b43_phy_maskset(dev, 0x0003, 0xFF9F, 0x0040); in b43_calc_nrssi_offset()
512 b43_radio_set(dev, 0x007A, 0x000F); in b43_calc_nrssi_offset()
513 b43_set_all_gains(dev, 3, 0, 1); in b43_calc_nrssi_offset()
514 b43_radio_maskset(dev, 0x0043, 0x00F0, 0x000F); in b43_calc_nrssi_offset()
516 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F); in b43_calc_nrssi_offset()
521 b43_radio_write16(dev, 0x007B, i); in b43_calc_nrssi_offset()
524 (s16) ((b43_phy_read(dev, 0x047F) >> 8) & in b43_calc_nrssi_offset()
536 b43_radio_write16(dev, 0x007B, saved); in b43_calc_nrssi_offset()
539 b43_phy_write(dev, 0x002E, backup[12]); in b43_calc_nrssi_offset()
540 b43_phy_write(dev, 0x002F, backup[13]); in b43_calc_nrssi_offset()
541 b43_phy_write(dev, 0x080F, backup[14]); in b43_calc_nrssi_offset()
542 b43_phy_write(dev, 0x0810, backup[15]); in b43_calc_nrssi_offset()
545 b43_phy_write(dev, 0x0814, backup[3]); in b43_calc_nrssi_offset()
546 b43_phy_write(dev, 0x0815, backup[4]); in b43_calc_nrssi_offset()
548 b43_phy_write(dev, 0x005A, backup[5]); in b43_calc_nrssi_offset()
549 b43_phy_write(dev, 0x0059, backup[6]); in b43_calc_nrssi_offset()
550 b43_phy_write(dev, 0x0058, backup[7]); in b43_calc_nrssi_offset()
551 b43_phy_write(dev, 0x000A, backup[8]); in b43_calc_nrssi_offset()
552 b43_phy_write(dev, 0x0003, backup[9]); in b43_calc_nrssi_offset()
553 b43_radio_write16(dev, 0x0043, backup[11]); in b43_calc_nrssi_offset()
554 b43_radio_write16(dev, 0x007A, backup[10]); in b43_calc_nrssi_offset()
555 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x1 | 0x2); in b43_calc_nrssi_offset()
556 b43_phy_set(dev, 0x0429, 0x8000); in b43_calc_nrssi_offset()
557 b43_set_original_gains(dev); in b43_calc_nrssi_offset()
559 b43_phy_write(dev, 0x0801, backup[16]); in b43_calc_nrssi_offset()
560 b43_phy_write(dev, 0x0060, backup[17]); in b43_calc_nrssi_offset()
561 b43_phy_write(dev, 0x0014, backup[18]); in b43_calc_nrssi_offset()
562 b43_phy_write(dev, 0x0478, backup[19]); in b43_calc_nrssi_offset()
564 b43_phy_write(dev, 0x0001, backup[0]); in b43_calc_nrssi_offset()
565 b43_phy_write(dev, 0x0812, backup[2]); in b43_calc_nrssi_offset()
566 b43_phy_write(dev, 0x0811, backup[1]); in b43_calc_nrssi_offset()
569 static void b43_calc_nrssi_slope(struct b43_wldev *dev) in b43_calc_nrssi_slope() argument
571 struct b43_phy *phy = &dev->phy; in b43_calc_nrssi_slope()
582 b43_calc_nrssi_offset(dev); in b43_calc_nrssi_slope()
584 b43_phy_mask(dev, B43_PHY_G_CRS, 0x7FFF); in b43_calc_nrssi_slope()
585 b43_phy_mask(dev, 0x0802, 0xFFFC); in b43_calc_nrssi_slope()
586 backup[7] = b43_read16(dev, 0x03E2); in b43_calc_nrssi_slope()
587 b43_write16(dev, 0x03E2, b43_read16(dev, 0x03E2) | 0x8000); in b43_calc_nrssi_slope()
588 backup[0] = b43_radio_read16(dev, 0x007A); in b43_calc_nrssi_slope()
589 backup[1] = b43_radio_read16(dev, 0x0052); in b43_calc_nrssi_slope()
590 backup[2] = b43_radio_read16(dev, 0x0043); in b43_calc_nrssi_slope()
591 backup[3] = b43_phy_read(dev, 0x0015); in b43_calc_nrssi_slope()
592 backup[4] = b43_phy_read(dev, 0x005A); in b43_calc_nrssi_slope()
593 backup[5] = b43_phy_read(dev, 0x0059); in b43_calc_nrssi_slope()
594 backup[6] = b43_phy_read(dev, 0x0058); in b43_calc_nrssi_slope()
595 backup[8] = b43_read16(dev, 0x03E6); in b43_calc_nrssi_slope()
596 backup[9] = b43_read16(dev, B43_MMIO_CHANNEL_EXT); in b43_calc_nrssi_slope()
598 backup[10] = b43_phy_read(dev, 0x002E); in b43_calc_nrssi_slope()
599 backup[11] = b43_phy_read(dev, 0x002F); in b43_calc_nrssi_slope()
600 backup[12] = b43_phy_read(dev, 0x080F); in b43_calc_nrssi_slope()
601 backup[13] = b43_phy_read(dev, B43_PHY_G_LO_CONTROL); in b43_calc_nrssi_slope()
602 backup[14] = b43_phy_read(dev, 0x0801); in b43_calc_nrssi_slope()
603 backup[15] = b43_phy_read(dev, 0x0060); in b43_calc_nrssi_slope()
604 backup[16] = b43_phy_read(dev, 0x0014); in b43_calc_nrssi_slope()
605 backup[17] = b43_phy_read(dev, 0x0478); in b43_calc_nrssi_slope()
606 b43_phy_write(dev, 0x002E, 0); in b43_calc_nrssi_slope()
607 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, 0); in b43_calc_nrssi_slope()
612 b43_phy_set(dev, 0x0478, 0x0100); in b43_calc_nrssi_slope()
613 b43_phy_set(dev, 0x0801, 0x0040); in b43_calc_nrssi_slope()
617 b43_phy_mask(dev, 0x0801, 0xFFBF); in b43_calc_nrssi_slope()
620 b43_phy_set(dev, 0x0060, 0x0040); in b43_calc_nrssi_slope()
621 b43_phy_set(dev, 0x0014, 0x0200); in b43_calc_nrssi_slope()
623 b43_radio_set(dev, 0x007A, 0x0070); in b43_calc_nrssi_slope()
624 b43_set_all_gains(dev, 0, 8, 0); in b43_calc_nrssi_slope()
625 b43_radio_mask(dev, 0x007A, 0x00F7); in b43_calc_nrssi_slope()
627 b43_phy_maskset(dev, 0x0811, 0xFFCF, 0x0030); in b43_calc_nrssi_slope()
628 b43_phy_maskset(dev, 0x0812, 0xFFCF, 0x0010); in b43_calc_nrssi_slope()
630 b43_radio_set(dev, 0x007A, 0x0080); in b43_calc_nrssi_slope()
633 nrssi0 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F); in b43_calc_nrssi_slope()
637 b43_radio_mask(dev, 0x007A, 0x007F); in b43_calc_nrssi_slope()
639 b43_phy_maskset(dev, 0x0003, 0xFF9F, 0x0040); in b43_calc_nrssi_slope()
642 b43_write16(dev, B43_MMIO_CHANNEL_EXT, in b43_calc_nrssi_slope()
643 b43_read16(dev, B43_MMIO_CHANNEL_EXT) in b43_calc_nrssi_slope()
645 b43_radio_set(dev, 0x007A, 0x000F); in b43_calc_nrssi_slope()
646 b43_phy_write(dev, 0x0015, 0xF330); in b43_calc_nrssi_slope()
648 b43_phy_maskset(dev, 0x0812, 0xFFCF, 0x0020); in b43_calc_nrssi_slope()
649 b43_phy_maskset(dev, 0x0811, 0xFFCF, 0x0020); in b43_calc_nrssi_slope()
652 b43_set_all_gains(dev, 3, 0, 1); in b43_calc_nrssi_slope()
654 b43_radio_write16(dev, 0x0043, 0x001F); in b43_calc_nrssi_slope()
656 tmp = b43_radio_read16(dev, 0x0052) & 0xFF0F; in b43_calc_nrssi_slope()
657 b43_radio_write16(dev, 0x0052, tmp | 0x0060); in b43_calc_nrssi_slope()
658 tmp = b43_radio_read16(dev, 0x0043) & 0xFFF0; in b43_calc_nrssi_slope()
659 b43_radio_write16(dev, 0x0043, tmp | 0x0009); in b43_calc_nrssi_slope()
661 b43_phy_write(dev, 0x005A, 0x0480); in b43_calc_nrssi_slope()
662 b43_phy_write(dev, 0x0059, 0x0810); in b43_calc_nrssi_slope()
663 b43_phy_write(dev, 0x0058, 0x000D); in b43_calc_nrssi_slope()
665 nrssi1 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F); in b43_calc_nrssi_slope()
677 b43_phy_write(dev, 0x002E, backup[10]); in b43_calc_nrssi_slope()
678 b43_phy_write(dev, 0x002F, backup[11]); in b43_calc_nrssi_slope()
679 b43_phy_write(dev, 0x080F, backup[12]); in b43_calc_nrssi_slope()
680 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, backup[13]); in b43_calc_nrssi_slope()
683 b43_phy_mask(dev, 0x0812, 0xFFCF); in b43_calc_nrssi_slope()
684 b43_phy_mask(dev, 0x0811, 0xFFCF); in b43_calc_nrssi_slope()
687 b43_radio_write16(dev, 0x007A, backup[0]); in b43_calc_nrssi_slope()
688 b43_radio_write16(dev, 0x0052, backup[1]); in b43_calc_nrssi_slope()
689 b43_radio_write16(dev, 0x0043, backup[2]); in b43_calc_nrssi_slope()
690 b43_write16(dev, 0x03E2, backup[7]); in b43_calc_nrssi_slope()
691 b43_write16(dev, 0x03E6, backup[8]); in b43_calc_nrssi_slope()
692 b43_write16(dev, B43_MMIO_CHANNEL_EXT, backup[9]); in b43_calc_nrssi_slope()
693 b43_phy_write(dev, 0x0015, backup[3]); in b43_calc_nrssi_slope()
694 b43_phy_write(dev, 0x005A, backup[4]); in b43_calc_nrssi_slope()
695 b43_phy_write(dev, 0x0059, backup[5]); in b43_calc_nrssi_slope()
696 b43_phy_write(dev, 0x0058, backup[6]); in b43_calc_nrssi_slope()
697 b43_synth_pu_workaround(dev, phy->channel); in b43_calc_nrssi_slope()
698 b43_phy_set(dev, 0x0802, (0x0001 | 0x0002)); in b43_calc_nrssi_slope()
699 b43_set_original_gains(dev); in b43_calc_nrssi_slope()
700 b43_phy_set(dev, B43_PHY_G_CRS, 0x8000); in b43_calc_nrssi_slope()
702 b43_phy_write(dev, 0x0801, backup[14]); in b43_calc_nrssi_slope()
703 b43_phy_write(dev, 0x0060, backup[15]); in b43_calc_nrssi_slope()
704 b43_phy_write(dev, 0x0014, backup[16]); in b43_calc_nrssi_slope()
705 b43_phy_write(dev, 0x0478, backup[17]); in b43_calc_nrssi_slope()
707 b43_nrssi_mem_update(dev); in b43_calc_nrssi_slope()
708 b43_calc_nrssi_threshold(dev); in b43_calc_nrssi_slope()
711 static void b43_calc_nrssi_threshold(struct b43_wldev *dev) in b43_calc_nrssi_threshold() argument
713 struct b43_phy *phy = &dev->phy; in b43_calc_nrssi_threshold()
722 !(dev->dev->bus_sprom->boardflags_lo & B43_BFL_RSSI)) { in b43_calc_nrssi_threshold()
723 tmp16 = b43_nrssi_hw_read(dev, 0x20); in b43_calc_nrssi_threshold()
727 b43_phy_maskset(dev, 0x048A, 0xF000, 0x09EB); in b43_calc_nrssi_threshold()
729 b43_phy_maskset(dev, 0x048A, 0xF000, 0x0AED); in b43_calc_nrssi_threshold()
761 tmp_u16 = b43_phy_read(dev, 0x048A) & 0xF000; in b43_calc_nrssi_threshold()
764 b43_phy_write(dev, 0x048A, tmp_u16); in b43_calc_nrssi_threshold()
807 b43_phy_read(dev, (offset))); \
811 b43_phy_write(dev, (offset), \
818 b43_radio_read16(dev, (offset))); \
822 b43_radio_write16(dev, (offset), \
829 b43_ofdmtab_read16(dev, (table), (offset))); \
833 b43_ofdmtab_write16(dev, (table), (offset), \
839 b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode) in b43_radio_interference_mitigation_enable() argument
841 struct b43_phy *phy = &dev->phy; in b43_radio_interference_mitigation_enable()
850 b43_phy_set(dev, 0x042B, 0x0800); in b43_radio_interference_mitigation_enable()
851 b43_phy_mask(dev, B43_PHY_G_CRS, ~0x4000); in b43_radio_interference_mitigation_enable()
855 tmp = (b43_radio_read16(dev, 0x0078) & 0x001E); in b43_radio_interference_mitigation_enable()
863 b43_radio_write16(dev, 0x0078, flipped); in b43_radio_interference_mitigation_enable()
865 b43_calc_nrssi_threshold(dev); in b43_radio_interference_mitigation_enable()
868 b43_phy_write(dev, 0x0406, 0x7E28); in b43_radio_interference_mitigation_enable()
870 b43_phy_set(dev, 0x042B, 0x0800); in b43_radio_interference_mitigation_enable()
871 b43_phy_set(dev, B43_PHY_RADIO_BITFIELD, 0x1000); in b43_radio_interference_mitigation_enable()
874 b43_phy_maskset(dev, 0x04A0, 0xC0C0, 0x0008); in b43_radio_interference_mitigation_enable()
876 b43_phy_maskset(dev, 0x04A1, 0xC0C0, 0x0605); in b43_radio_interference_mitigation_enable()
878 b43_phy_maskset(dev, 0x04A2, 0xC0C0, 0x0204); in b43_radio_interference_mitigation_enable()
880 b43_phy_maskset(dev, 0x04A8, 0xC0C0, 0x0803); in b43_radio_interference_mitigation_enable()
882 b43_phy_maskset(dev, 0x04AB, 0xC0C0, 0x0605); in b43_radio_interference_mitigation_enable()
885 b43_phy_write(dev, 0x04A7, 0x0002); in b43_radio_interference_mitigation_enable()
887 b43_phy_write(dev, 0x04A3, 0x287A); in b43_radio_interference_mitigation_enable()
889 b43_phy_write(dev, 0x04A9, 0x2027); in b43_radio_interference_mitigation_enable()
891 b43_phy_write(dev, 0x0493, 0x32F5); in b43_radio_interference_mitigation_enable()
893 b43_phy_write(dev, 0x04AA, 0x2027); in b43_radio_interference_mitigation_enable()
895 b43_phy_write(dev, 0x04AC, 0x32F5); in b43_radio_interference_mitigation_enable()
898 if (b43_phy_read(dev, 0x0033) & 0x0800) in b43_radio_interference_mitigation_enable()
938 b43_phy_mask(dev, B43_PHY_RADIO_BITFIELD, ~0x1000); in b43_radio_interference_mitigation_enable()
939 b43_phy_maskset(dev, B43_PHY_G_CRS, 0xFFFC, 0x0002); in b43_radio_interference_mitigation_enable()
941 b43_phy_write(dev, 0x0033, 0x0800); in b43_radio_interference_mitigation_enable()
942 b43_phy_write(dev, 0x04A3, 0x2027); in b43_radio_interference_mitigation_enable()
943 b43_phy_write(dev, 0x04A9, 0x1CA8); in b43_radio_interference_mitigation_enable()
944 b43_phy_write(dev, 0x0493, 0x287A); in b43_radio_interference_mitigation_enable()
945 b43_phy_write(dev, 0x04AA, 0x1CA8); in b43_radio_interference_mitigation_enable()
946 b43_phy_write(dev, 0x04AC, 0x287A); in b43_radio_interference_mitigation_enable()
948 b43_phy_maskset(dev, 0x04A0, 0xFFC0, 0x001A); in b43_radio_interference_mitigation_enable()
949 b43_phy_write(dev, 0x04A7, 0x000D); in b43_radio_interference_mitigation_enable()
952 b43_phy_write(dev, 0x0406, 0xFF0D); in b43_radio_interference_mitigation_enable()
954 b43_phy_write(dev, 0x04C0, 0xFFFF); in b43_radio_interference_mitigation_enable()
955 b43_phy_write(dev, 0x04C1, 0x00A9); in b43_radio_interference_mitigation_enable()
957 b43_phy_write(dev, 0x04C0, 0x00C1); in b43_radio_interference_mitigation_enable()
958 b43_phy_write(dev, 0x04C1, 0x0059); in b43_radio_interference_mitigation_enable()
961 b43_phy_maskset(dev, 0x04A1, 0xC0FF, 0x1800); in b43_radio_interference_mitigation_enable()
962 b43_phy_maskset(dev, 0x04A1, 0xFFC0, 0x0015); in b43_radio_interference_mitigation_enable()
963 b43_phy_maskset(dev, 0x04A8, 0xCFFF, 0x1000); in b43_radio_interference_mitigation_enable()
964 b43_phy_maskset(dev, 0x04A8, 0xF0FF, 0x0A00); in b43_radio_interference_mitigation_enable()
965 b43_phy_maskset(dev, 0x04AB, 0xCFFF, 0x1000); in b43_radio_interference_mitigation_enable()
966 b43_phy_maskset(dev, 0x04AB, 0xF0FF, 0x0800); in b43_radio_interference_mitigation_enable()
967 b43_phy_maskset(dev, 0x04AB, 0xFFCF, 0x0010); in b43_radio_interference_mitigation_enable()
968 b43_phy_maskset(dev, 0x04AB, 0xFFF0, 0x0005); in b43_radio_interference_mitigation_enable()
969 b43_phy_maskset(dev, 0x04A8, 0xFFCF, 0x0010); in b43_radio_interference_mitigation_enable()
970 b43_phy_maskset(dev, 0x04A8, 0xFFF0, 0x0006); in b43_radio_interference_mitigation_enable()
971 b43_phy_maskset(dev, 0x04A2, 0xF0FF, 0x0800); in b43_radio_interference_mitigation_enable()
972 b43_phy_maskset(dev, 0x04A0, 0xF0FF, 0x0500); in b43_radio_interference_mitigation_enable()
973 b43_phy_maskset(dev, 0x04A2, 0xFFF0, 0x000B); in b43_radio_interference_mitigation_enable()
976 b43_phy_mask(dev, 0x048A, 0x7FFF); in b43_radio_interference_mitigation_enable()
977 b43_phy_maskset(dev, 0x0415, 0x8000, 0x36D8); in b43_radio_interference_mitigation_enable()
978 b43_phy_maskset(dev, 0x0416, 0x8000, 0x36D8); in b43_radio_interference_mitigation_enable()
979 b43_phy_maskset(dev, 0x0417, 0xFE00, 0x016D); in b43_radio_interference_mitigation_enable()
981 b43_phy_set(dev, 0x048A, 0x1000); in b43_radio_interference_mitigation_enable()
982 b43_phy_maskset(dev, 0x048A, 0x9FFF, 0x2000); in b43_radio_interference_mitigation_enable()
983 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ACIW); in b43_radio_interference_mitigation_enable()
986 b43_phy_set(dev, 0x042B, 0x0800); in b43_radio_interference_mitigation_enable()
988 b43_phy_maskset(dev, 0x048C, 0xF0FF, 0x0200); in b43_radio_interference_mitigation_enable()
990 b43_phy_maskset(dev, 0x04AE, 0xFF00, 0x007F); in b43_radio_interference_mitigation_enable()
991 b43_phy_maskset(dev, 0x04AD, 0x00FF, 0x1300); in b43_radio_interference_mitigation_enable()
993 b43_ofdmtab_write16(dev, 0x1A00, 0x3, 0x007F); in b43_radio_interference_mitigation_enable()
994 b43_ofdmtab_write16(dev, 0x1A00, 0x2, 0x007F); in b43_radio_interference_mitigation_enable()
995 b43_phy_mask(dev, 0x04AD, 0x00FF); in b43_radio_interference_mitigation_enable()
997 b43_calc_nrssi_slope(dev); in b43_radio_interference_mitigation_enable()
1005 b43_radio_interference_mitigation_disable(struct b43_wldev *dev, int mode) in b43_radio_interference_mitigation_disable() argument
1007 struct b43_phy *phy = &dev->phy; in b43_radio_interference_mitigation_disable()
1014 b43_phy_mask(dev, 0x042B, ~0x0800); in b43_radio_interference_mitigation_disable()
1015 b43_phy_set(dev, B43_PHY_G_CRS, 0x4000); in b43_radio_interference_mitigation_disable()
1019 b43_calc_nrssi_threshold(dev); in b43_radio_interference_mitigation_disable()
1021 b43_phy_mask(dev, 0x042B, ~0x0800); in b43_radio_interference_mitigation_disable()
1022 if (!dev->bad_frames_preempt) { in b43_radio_interference_mitigation_disable()
1023 b43_phy_mask(dev, B43_PHY_RADIO_BITFIELD, ~(1 << 11)); in b43_radio_interference_mitigation_disable()
1025 b43_phy_set(dev, B43_PHY_G_CRS, 0x4000); in b43_radio_interference_mitigation_disable()
1039 if (!(b43_phy_read(dev, 0x0033) & 0x0800)) in b43_radio_interference_mitigation_disable()
1077 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ACIW); in b43_radio_interference_mitigation_disable()
1078 b43_calc_nrssi_slope(dev); in b43_radio_interference_mitigation_disable()
1092 static u16 b43_radio_core_calibration_value(struct b43_wldev *dev) in b43_radio_core_calibration_value() argument
1103 reg = b43_radio_read16(dev, 0x60); in b43_radio_core_calibration_value()
1113 static u16 radio2050_rfover_val(struct b43_wldev *dev, in radio2050_rfover_val() argument
1116 struct b43_phy *phy = &dev->phy; in radio2050_rfover_val()
1118 struct ssb_sprom *sprom = dev->dev->bus_sprom; in radio2050_rfover_val()
1258 static u16 b43_radio_init2050(struct b43_wldev *dev) in b43_radio_init2050() argument
1260 struct b43_phy *phy = &dev->phy; in b43_radio_init2050()
1270 sav.radio_43 = b43_radio_read16(dev, 0x43); in b43_radio_init2050()
1271 sav.radio_51 = b43_radio_read16(dev, 0x51); in b43_radio_init2050()
1272 sav.radio_52 = b43_radio_read16(dev, 0x52); in b43_radio_init2050()
1273 sav.phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL); in b43_radio_init2050()
1274 sav.phy_cck_5A = b43_phy_read(dev, B43_PHY_CCK(0x5A)); in b43_radio_init2050()
1275 sav.phy_cck_59 = b43_phy_read(dev, B43_PHY_CCK(0x59)); in b43_radio_init2050()
1276 sav.phy_cck_58 = b43_phy_read(dev, B43_PHY_CCK(0x58)); in b43_radio_init2050()
1279 sav.phy_cck_30 = b43_phy_read(dev, B43_PHY_CCK(0x30)); in b43_radio_init2050()
1280 sav.reg_3EC = b43_read16(dev, 0x3EC); in b43_radio_init2050()
1282 b43_phy_write(dev, B43_PHY_CCK(0x30), 0xFF); in b43_radio_init2050()
1283 b43_write16(dev, 0x3EC, 0x3F3F); in b43_radio_init2050()
1285 sav.phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER); in b43_radio_init2050()
1286 sav.phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL); in b43_radio_init2050()
1287 sav.phy_analogover = b43_phy_read(dev, B43_PHY_ANALOGOVER); in b43_radio_init2050()
1289 b43_phy_read(dev, B43_PHY_ANALOGOVERVAL); in b43_radio_init2050()
1290 sav.phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0); in b43_radio_init2050()
1291 sav.phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL); in b43_radio_init2050()
1293 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0003); in b43_radio_init2050()
1294 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFC); in b43_radio_init2050()
1295 b43_phy_mask(dev, B43_PHY_CRS0, 0x7FFF); in b43_radio_init2050()
1296 b43_phy_mask(dev, B43_PHY_CLASSCTL, 0xFFFC); in b43_radio_init2050()
1298 sav.phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK); in b43_radio_init2050()
1299 sav.phy_lo_ctl = b43_phy_read(dev, B43_PHY_LO_CTL); in b43_radio_init2050()
1302 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020); in b43_radio_init2050()
1304 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020); in b43_radio_init2050()
1305 b43_phy_write(dev, B43_PHY_LO_CTL, 0); in b43_radio_init2050()
1308 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1309 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1311 b43_phy_write(dev, B43_PHY_RFOVER, in b43_radio_init2050()
1312 radio2050_rfover_val(dev, B43_PHY_RFOVER, 0)); in b43_radio_init2050()
1314 b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2) | 0x8000); in b43_radio_init2050()
1316 sav.phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL); in b43_radio_init2050()
1317 b43_phy_mask(dev, B43_PHY_SYNCCTL, 0xFF7F); in b43_radio_init2050()
1318 sav.reg_3E6 = b43_read16(dev, 0x3E6); in b43_radio_init2050()
1319 sav.reg_3F4 = b43_read16(dev, 0x3F4); in b43_radio_init2050()
1322 b43_write16(dev, 0x03E6, 0x0122); in b43_radio_init2050()
1325 b43_phy_maskset(dev, B43_PHY_CCK(0x03), 0xFFBF, 0x40); in b43_radio_init2050()
1327 b43_write16(dev, B43_MMIO_CHANNEL_EXT, in b43_radio_init2050()
1328 (b43_read16(dev, B43_MMIO_CHANNEL_EXT) | 0x2000)); in b43_radio_init2050()
1331 rcc = b43_radio_core_calibration_value(dev); in b43_radio_init2050()
1334 b43_radio_write16(dev, 0x78, 0x26); in b43_radio_init2050()
1336 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1337 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1340 b43_phy_write(dev, B43_PHY_PGACTL, 0xBFAF); in b43_radio_init2050()
1341 b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x1403); in b43_radio_init2050()
1343 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1344 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1347 b43_phy_write(dev, B43_PHY_PGACTL, 0xBFA0); in b43_radio_init2050()
1348 b43_radio_set(dev, 0x51, 0x0004); in b43_radio_init2050()
1350 b43_radio_write16(dev, 0x43, 0x1F); in b43_radio_init2050()
1352 b43_radio_write16(dev, 0x52, 0); in b43_radio_init2050()
1353 b43_radio_maskset(dev, 0x43, 0xFFF0, 0x0009); in b43_radio_init2050()
1355 b43_phy_write(dev, B43_PHY_CCK(0x58), 0); in b43_radio_init2050()
1358 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0480); in b43_radio_init2050()
1359 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810); in b43_radio_init2050()
1360 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D); in b43_radio_init2050()
1362 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1363 radio2050_rfover_val(dev, in b43_radio_init2050()
1367 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0); in b43_radio_init2050()
1370 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1371 radio2050_rfover_val(dev, in b43_radio_init2050()
1375 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0); in b43_radio_init2050()
1378 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1379 radio2050_rfover_val(dev, in b43_radio_init2050()
1383 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0); in b43_radio_init2050()
1385 tmp1 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE); in b43_radio_init2050()
1386 b43_phy_write(dev, B43_PHY_CCK(0x58), 0); in b43_radio_init2050()
1388 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1389 radio2050_rfover_val(dev, in b43_radio_init2050()
1393 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0); in b43_radio_init2050()
1397 b43_phy_write(dev, B43_PHY_CCK(0x58), 0); in b43_radio_init2050()
1403 b43_radio_write16(dev, 0x78, radio78); in b43_radio_init2050()
1406 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0D80); in b43_radio_init2050()
1407 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810); in b43_radio_init2050()
1408 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D); in b43_radio_init2050()
1410 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1411 radio2050_rfover_val(dev, in b43_radio_init2050()
1416 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0); in b43_radio_init2050()
1419 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1420 radio2050_rfover_val(dev, in b43_radio_init2050()
1425 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0); in b43_radio_init2050()
1428 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1429 radio2050_rfover_val(dev, in b43_radio_init2050()
1434 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0); in b43_radio_init2050()
1436 tmp2 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE); in b43_radio_init2050()
1437 b43_phy_write(dev, B43_PHY_CCK(0x58), 0); in b43_radio_init2050()
1439 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1440 radio2050_rfover_val(dev, in b43_radio_init2050()
1445 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0); in b43_radio_init2050()
1454 b43_phy_write(dev, B43_PHY_PGACTL, sav.phy_pgactl); in b43_radio_init2050()
1455 b43_radio_write16(dev, 0x51, sav.radio_51); in b43_radio_init2050()
1456 b43_radio_write16(dev, 0x52, sav.radio_52); in b43_radio_init2050()
1457 b43_radio_write16(dev, 0x43, sav.radio_43); in b43_radio_init2050()
1458 b43_phy_write(dev, B43_PHY_CCK(0x5A), sav.phy_cck_5A); in b43_radio_init2050()
1459 b43_phy_write(dev, B43_PHY_CCK(0x59), sav.phy_cck_59); in b43_radio_init2050()
1460 b43_phy_write(dev, B43_PHY_CCK(0x58), sav.phy_cck_58); in b43_radio_init2050()
1461 b43_write16(dev, 0x3E6, sav.reg_3E6); in b43_radio_init2050()
1463 b43_write16(dev, 0x3F4, sav.reg_3F4); in b43_radio_init2050()
1464 b43_phy_write(dev, B43_PHY_SYNCCTL, sav.phy_syncctl); in b43_radio_init2050()
1465 b43_synth_pu_workaround(dev, phy->channel); in b43_radio_init2050()
1467 b43_phy_write(dev, B43_PHY_CCK(0x30), sav.phy_cck_30); in b43_radio_init2050()
1468 b43_write16(dev, 0x3EC, sav.reg_3EC); in b43_radio_init2050()
1470 b43_write16(dev, B43_MMIO_PHY_RADIO, in b43_radio_init2050()
1471 b43_read16(dev, B43_MMIO_PHY_RADIO) in b43_radio_init2050()
1473 b43_phy_write(dev, B43_PHY_RFOVER, sav.phy_rfover); in b43_radio_init2050()
1474 b43_phy_write(dev, B43_PHY_RFOVERVAL, sav.phy_rfoverval); in b43_radio_init2050()
1475 b43_phy_write(dev, B43_PHY_ANALOGOVER, sav.phy_analogover); in b43_radio_init2050()
1476 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, in b43_radio_init2050()
1478 b43_phy_write(dev, B43_PHY_CRS0, sav.phy_crs0); in b43_radio_init2050()
1479 b43_phy_write(dev, B43_PHY_CLASSCTL, sav.phy_classctl); in b43_radio_init2050()
1481 b43_phy_write(dev, B43_PHY_LO_MASK, sav.phy_lo_mask); in b43_radio_init2050()
1482 b43_phy_write(dev, B43_PHY_LO_CTL, sav.phy_lo_ctl); in b43_radio_init2050()
1493 static void b43_phy_initb5(struct b43_wldev *dev) in b43_phy_initb5() argument
1495 struct b43_phy *phy = &dev->phy; in b43_phy_initb5()
1501 b43_radio_set(dev, 0x007A, 0x0050); in b43_phy_initb5()
1503 if ((dev->dev->board_vendor != SSB_BOARDVENDOR_BCM) && in b43_phy_initb5()
1504 (dev->dev->board_type != SSB_BOARD_BU4306)) { in b43_phy_initb5()
1507 b43_phy_write(dev, offset, value); in b43_phy_initb5()
1511 b43_phy_maskset(dev, 0x0035, 0xF0FF, 0x0700); in b43_phy_initb5()
1513 b43_phy_write(dev, 0x0038, 0x0667); in b43_phy_initb5()
1517 b43_radio_set(dev, 0x007A, 0x0020); in b43_phy_initb5()
1518 b43_radio_set(dev, 0x0051, 0x0004); in b43_phy_initb5()
1520 b43_write16(dev, B43_MMIO_PHY_RADIO, 0x0000); in b43_phy_initb5()
1522 b43_phy_set(dev, 0x0802, 0x0100); in b43_phy_initb5()
1523 b43_phy_set(dev, 0x042B, 0x2000); in b43_phy_initb5()
1525 b43_phy_write(dev, 0x001C, 0x186A); in b43_phy_initb5()
1527 b43_phy_maskset(dev, 0x0013, 0x00FF, 0x1900); in b43_phy_initb5()
1528 b43_phy_maskset(dev, 0x0035, 0xFFC0, 0x0064); in b43_phy_initb5()
1529 b43_phy_maskset(dev, 0x005D, 0xFF80, 0x000A); in b43_phy_initb5()
1532 if (dev->bad_frames_preempt) { in b43_phy_initb5()
1533 b43_phy_set(dev, B43_PHY_RADIO_BITFIELD, (1 << 11)); in b43_phy_initb5()
1537 b43_phy_write(dev, 0x0026, 0xCE00); in b43_phy_initb5()
1538 b43_phy_write(dev, 0x0021, 0x3763); in b43_phy_initb5()
1539 b43_phy_write(dev, 0x0022, 0x1BC3); in b43_phy_initb5()
1540 b43_phy_write(dev, 0x0023, 0x06F9); in b43_phy_initb5()
1541 b43_phy_write(dev, 0x0024, 0x037E); in b43_phy_initb5()
1543 b43_phy_write(dev, 0x0026, 0xCC00); in b43_phy_initb5()
1544 b43_phy_write(dev, 0x0030, 0x00C6); in b43_phy_initb5()
1545 b43_write16(dev, 0x03EC, 0x3F22); in b43_phy_initb5()
1548 b43_phy_write(dev, 0x0020, 0x3E1C); in b43_phy_initb5()
1550 b43_phy_write(dev, 0x0020, 0x301C); in b43_phy_initb5()
1553 b43_write16(dev, 0x03E4, 0x3000); in b43_phy_initb5()
1557 b43_gphy_channel_switch(dev, 7, 0); in b43_phy_initb5()
1560 b43_radio_write16(dev, 0x0075, 0x0080); in b43_phy_initb5()
1561 b43_radio_write16(dev, 0x0079, 0x0081); in b43_phy_initb5()
1564 b43_radio_write16(dev, 0x0050, 0x0020); in b43_phy_initb5()
1565 b43_radio_write16(dev, 0x0050, 0x0023); in b43_phy_initb5()
1568 b43_radio_write16(dev, 0x0050, 0x0020); in b43_phy_initb5()
1569 b43_radio_write16(dev, 0x005A, 0x0070); in b43_phy_initb5()
1572 b43_radio_write16(dev, 0x005B, 0x007B); in b43_phy_initb5()
1573 b43_radio_write16(dev, 0x005C, 0x00B0); in b43_phy_initb5()
1575 b43_radio_set(dev, 0x007A, 0x0007); in b43_phy_initb5()
1577 b43_gphy_channel_switch(dev, old_channel, 0); in b43_phy_initb5()
1579 b43_phy_write(dev, 0x0014, 0x0080); in b43_phy_initb5()
1580 b43_phy_write(dev, 0x0032, 0x00CA); in b43_phy_initb5()
1581 b43_phy_write(dev, 0x002A, 0x88A3); in b43_phy_initb5()
1583 b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, gphy->tx_control); in b43_phy_initb5()
1586 b43_radio_write16(dev, 0x005D, 0x000D); in b43_phy_initb5()
1588 b43_write16(dev, 0x03E4, (b43_read16(dev, 0x03E4) & 0xFFC0) | 0x0004); in b43_phy_initb5()
1592 static void b43_phy_initb6(struct b43_wldev *dev) in b43_phy_initb6() argument
1594 struct b43_phy *phy = &dev->phy; in b43_phy_initb6()
1599 b43_phy_write(dev, 0x003E, 0x817A); in b43_phy_initb6()
1600 b43_radio_write16(dev, 0x007A, in b43_phy_initb6()
1601 (b43_radio_read16(dev, 0x007A) | 0x0058)); in b43_phy_initb6()
1603 b43_radio_write16(dev, 0x51, 0x37); in b43_phy_initb6()
1604 b43_radio_write16(dev, 0x52, 0x70); in b43_phy_initb6()
1605 b43_radio_write16(dev, 0x53, 0xB3); in b43_phy_initb6()
1606 b43_radio_write16(dev, 0x54, 0x9B); in b43_phy_initb6()
1607 b43_radio_write16(dev, 0x5A, 0x88); in b43_phy_initb6()
1608 b43_radio_write16(dev, 0x5B, 0x88); in b43_phy_initb6()
1609 b43_radio_write16(dev, 0x5D, 0x88); in b43_phy_initb6()
1610 b43_radio_write16(dev, 0x5E, 0x88); in b43_phy_initb6()
1611 b43_radio_write16(dev, 0x7D, 0x88); in b43_phy_initb6()
1612 b43_hf_write(dev, b43_hf_read(dev) in b43_phy_initb6()
1617 b43_radio_write16(dev, 0x51, 0); in b43_phy_initb6()
1618 b43_radio_write16(dev, 0x52, 0x40); in b43_phy_initb6()
1619 b43_radio_write16(dev, 0x53, 0xB7); in b43_phy_initb6()
1620 b43_radio_write16(dev, 0x54, 0x98); in b43_phy_initb6()
1621 b43_radio_write16(dev, 0x5A, 0x88); in b43_phy_initb6()
1622 b43_radio_write16(dev, 0x5B, 0x6B); in b43_phy_initb6()
1623 b43_radio_write16(dev, 0x5C, 0x0F); in b43_phy_initb6()
1624 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_ALTIQ) { in b43_phy_initb6()
1625 b43_radio_write16(dev, 0x5D, 0xFA); in b43_phy_initb6()
1626 b43_radio_write16(dev, 0x5E, 0xD8); in b43_phy_initb6()
1628 b43_radio_write16(dev, 0x5D, 0xF5); in b43_phy_initb6()
1629 b43_radio_write16(dev, 0x5E, 0xB8); in b43_phy_initb6()
1631 b43_radio_write16(dev, 0x0073, 0x0003); in b43_phy_initb6()
1632 b43_radio_write16(dev, 0x007D, 0x00A8); in b43_phy_initb6()
1633 b43_radio_write16(dev, 0x007C, 0x0001); in b43_phy_initb6()
1634 b43_radio_write16(dev, 0x007E, 0x0008); in b43_phy_initb6()
1638 b43_phy_write(dev, offset, val); in b43_phy_initb6()
1643 b43_phy_write(dev, offset, val); in b43_phy_initb6()
1648 b43_phy_write(dev, offset, (val & 0x3F3F)); in b43_phy_initb6()
1652 b43_radio_set(dev, 0x007A, 0x0020); in b43_phy_initb6()
1653 b43_radio_set(dev, 0x0051, 0x0004); in b43_phy_initb6()
1654 b43_phy_set(dev, 0x0802, 0x0100); in b43_phy_initb6()
1655 b43_phy_set(dev, 0x042B, 0x2000); in b43_phy_initb6()
1656 b43_phy_write(dev, 0x5B, 0); in b43_phy_initb6()
1657 b43_phy_write(dev, 0x5C, 0); in b43_phy_initb6()
1662 b43_gphy_channel_switch(dev, 1, 0); in b43_phy_initb6()
1664 b43_gphy_channel_switch(dev, 13, 0); in b43_phy_initb6()
1666 b43_radio_write16(dev, 0x0050, 0x0020); in b43_phy_initb6()
1667 b43_radio_write16(dev, 0x0050, 0x0023); in b43_phy_initb6()
1670 b43_radio_write16(dev, 0x7C, (b43_radio_read16(dev, 0x7C) in b43_phy_initb6()
1672 b43_radio_write16(dev, 0x50, 0x20); in b43_phy_initb6()
1675 b43_radio_write16(dev, 0x50, 0x20); in b43_phy_initb6()
1676 b43_radio_write16(dev, 0x5A, 0x70); in b43_phy_initb6()
1677 b43_radio_write16(dev, 0x5B, 0x7B); in b43_phy_initb6()
1678 b43_radio_write16(dev, 0x5C, 0xB0); in b43_phy_initb6()
1680 b43_radio_maskset(dev, 0x007A, 0x00F8, 0x0007); in b43_phy_initb6()
1682 b43_gphy_channel_switch(dev, old_channel, 0); in b43_phy_initb6()
1684 b43_phy_write(dev, 0x0014, 0x0200); in b43_phy_initb6()
1686 b43_phy_write(dev, 0x2A, 0x88C2); in b43_phy_initb6()
1688 b43_phy_write(dev, 0x2A, 0x8AC0); in b43_phy_initb6()
1689 b43_phy_write(dev, 0x0038, 0x0668); in b43_phy_initb6()
1690 b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, gphy->tx_control); in b43_phy_initb6()
1692 b43_phy_maskset(dev, 0x5D, 0xFF80, 0x0003); in b43_phy_initb6()
1694 b43_radio_write16(dev, 0x005D, 0x000D); in b43_phy_initb6()
1697 b43_write16(dev, 0x3E4, 9); in b43_phy_initb6()
1698 b43_phy_mask(dev, 0x61, 0x0FFF); in b43_phy_initb6()
1700 b43_phy_maskset(dev, 0x0002, 0xFFC0, 0x0004); in b43_phy_initb6()
1705 b43_write16(dev, 0x03E6, 0x0); in b43_phy_initb6()
1708 static void b43_calc_loopback_gain(struct b43_wldev *dev) in b43_calc_loopback_gain() argument
1710 struct b43_phy *phy = &dev->phy; in b43_calc_loopback_gain()
1719 backup_phy[0] = b43_phy_read(dev, B43_PHY_CRS0); in b43_calc_loopback_gain()
1720 backup_phy[1] = b43_phy_read(dev, B43_PHY_CCKBBANDCFG); in b43_calc_loopback_gain()
1721 backup_phy[2] = b43_phy_read(dev, B43_PHY_RFOVER); in b43_calc_loopback_gain()
1722 backup_phy[3] = b43_phy_read(dev, B43_PHY_RFOVERVAL); in b43_calc_loopback_gain()
1724 backup_phy[4] = b43_phy_read(dev, B43_PHY_ANALOGOVER); in b43_calc_loopback_gain()
1725 backup_phy[5] = b43_phy_read(dev, B43_PHY_ANALOGOVERVAL); in b43_calc_loopback_gain()
1727 backup_phy[6] = b43_phy_read(dev, B43_PHY_CCK(0x5A)); in b43_calc_loopback_gain()
1728 backup_phy[7] = b43_phy_read(dev, B43_PHY_CCK(0x59)); in b43_calc_loopback_gain()
1729 backup_phy[8] = b43_phy_read(dev, B43_PHY_CCK(0x58)); in b43_calc_loopback_gain()
1730 backup_phy[9] = b43_phy_read(dev, B43_PHY_CCK(0x0A)); in b43_calc_loopback_gain()
1731 backup_phy[10] = b43_phy_read(dev, B43_PHY_CCK(0x03)); in b43_calc_loopback_gain()
1732 backup_phy[11] = b43_phy_read(dev, B43_PHY_LO_MASK); in b43_calc_loopback_gain()
1733 backup_phy[12] = b43_phy_read(dev, B43_PHY_LO_CTL); in b43_calc_loopback_gain()
1734 backup_phy[13] = b43_phy_read(dev, B43_PHY_CCK(0x2B)); in b43_calc_loopback_gain()
1735 backup_phy[14] = b43_phy_read(dev, B43_PHY_PGACTL); in b43_calc_loopback_gain()
1736 backup_phy[15] = b43_phy_read(dev, B43_PHY_LO_LEAKAGE); in b43_calc_loopback_gain()
1738 backup_radio[0] = b43_radio_read16(dev, 0x52); in b43_calc_loopback_gain()
1739 backup_radio[1] = b43_radio_read16(dev, 0x43); in b43_calc_loopback_gain()
1740 backup_radio[2] = b43_radio_read16(dev, 0x7A); in b43_calc_loopback_gain()
1742 b43_phy_mask(dev, B43_PHY_CRS0, 0x3FFF); in b43_calc_loopback_gain()
1743 b43_phy_set(dev, B43_PHY_CCKBBANDCFG, 0x8000); in b43_calc_loopback_gain()
1744 b43_phy_set(dev, B43_PHY_RFOVER, 0x0002); in b43_calc_loopback_gain()
1745 b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xFFFD); in b43_calc_loopback_gain()
1746 b43_phy_set(dev, B43_PHY_RFOVER, 0x0001); in b43_calc_loopback_gain()
1747 b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xFFFE); in b43_calc_loopback_gain()
1749 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0001); in b43_calc_loopback_gain()
1750 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFE); in b43_calc_loopback_gain()
1751 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0002); in b43_calc_loopback_gain()
1752 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFD); in b43_calc_loopback_gain()
1754 b43_phy_set(dev, B43_PHY_RFOVER, 0x000C); in b43_calc_loopback_gain()
1755 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x000C); in b43_calc_loopback_gain()
1756 b43_phy_set(dev, B43_PHY_RFOVER, 0x0030); in b43_calc_loopback_gain()
1757 b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xFFCF, 0x10); in b43_calc_loopback_gain()
1759 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0780); in b43_calc_loopback_gain()
1760 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810); in b43_calc_loopback_gain()
1761 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D); in b43_calc_loopback_gain()
1763 b43_phy_set(dev, B43_PHY_CCK(0x0A), 0x2000); in b43_calc_loopback_gain()
1765 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0004); in b43_calc_loopback_gain()
1766 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFB); in b43_calc_loopback_gain()
1768 b43_phy_maskset(dev, B43_PHY_CCK(0x03), 0xFF9F, 0x40); in b43_calc_loopback_gain()
1771 b43_radio_write16(dev, 0x43, 0x000F); in b43_calc_loopback_gain()
1773 b43_radio_write16(dev, 0x52, 0); in b43_calc_loopback_gain()
1774 b43_radio_maskset(dev, 0x43, 0xFFF0, 0x9); in b43_calc_loopback_gain()
1776 b43_gphy_set_baseband_attenuation(dev, 11); in b43_calc_loopback_gain()
1779 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020); in b43_calc_loopback_gain()
1781 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020); in b43_calc_loopback_gain()
1782 b43_phy_write(dev, B43_PHY_LO_CTL, 0); in b43_calc_loopback_gain()
1784 b43_phy_maskset(dev, B43_PHY_CCK(0x2B), 0xFFC0, 0x01); in b43_calc_loopback_gain()
1785 b43_phy_maskset(dev, B43_PHY_CCK(0x2B), 0xC0FF, 0x800); in b43_calc_loopback_gain()
1787 b43_phy_set(dev, B43_PHY_RFOVER, 0x0100); in b43_calc_loopback_gain()
1788 b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xCFFF); in b43_calc_loopback_gain()
1790 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_EXTLNA) { in b43_calc_loopback_gain()
1792 b43_phy_set(dev, B43_PHY_RFOVER, 0x0800); in b43_calc_loopback_gain()
1793 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x8000); in b43_calc_loopback_gain()
1796 b43_radio_mask(dev, 0x7A, 0x00F7); in b43_calc_loopback_gain()
1802 b43_radio_write16(dev, 0x43, i); in b43_calc_loopback_gain()
1803 b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xF0FF, (j << 8)); in b43_calc_loopback_gain()
1804 b43_phy_maskset(dev, B43_PHY_PGACTL, 0x0FFF, 0xA000); in b43_calc_loopback_gain()
1805 b43_phy_set(dev, B43_PHY_PGACTL, 0xF000); in b43_calc_loopback_gain()
1807 if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC) in b43_calc_loopback_gain()
1815 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x30); in b43_calc_loopback_gain()
1818 b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xF0FF, (j << 8)); in b43_calc_loopback_gain()
1819 b43_phy_maskset(dev, B43_PHY_PGACTL, 0x0FFF, 0xA000); in b43_calc_loopback_gain()
1820 b43_phy_set(dev, B43_PHY_PGACTL, 0xF000); in b43_calc_loopback_gain()
1823 if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC) in b43_calc_loopback_gain()
1831 b43_phy_write(dev, B43_PHY_ANALOGOVER, backup_phy[4]); in b43_calc_loopback_gain()
1832 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, backup_phy[5]); in b43_calc_loopback_gain()
1834 b43_phy_write(dev, B43_PHY_CCK(0x5A), backup_phy[6]); in b43_calc_loopback_gain()
1835 b43_phy_write(dev, B43_PHY_CCK(0x59), backup_phy[7]); in b43_calc_loopback_gain()
1836 b43_phy_write(dev, B43_PHY_CCK(0x58), backup_phy[8]); in b43_calc_loopback_gain()
1837 b43_phy_write(dev, B43_PHY_CCK(0x0A), backup_phy[9]); in b43_calc_loopback_gain()
1838 b43_phy_write(dev, B43_PHY_CCK(0x03), backup_phy[10]); in b43_calc_loopback_gain()
1839 b43_phy_write(dev, B43_PHY_LO_MASK, backup_phy[11]); in b43_calc_loopback_gain()
1840 b43_phy_write(dev, B43_PHY_LO_CTL, backup_phy[12]); in b43_calc_loopback_gain()
1841 b43_phy_write(dev, B43_PHY_CCK(0x2B), backup_phy[13]); in b43_calc_loopback_gain()
1842 b43_phy_write(dev, B43_PHY_PGACTL, backup_phy[14]); in b43_calc_loopback_gain()
1844 b43_gphy_set_baseband_attenuation(dev, backup_bband); in b43_calc_loopback_gain()
1846 b43_radio_write16(dev, 0x52, backup_radio[0]); in b43_calc_loopback_gain()
1847 b43_radio_write16(dev, 0x43, backup_radio[1]); in b43_calc_loopback_gain()
1848 b43_radio_write16(dev, 0x7A, backup_radio[2]); in b43_calc_loopback_gain()
1850 b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2] | 0x0003); in b43_calc_loopback_gain()
1852 b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2]); in b43_calc_loopback_gain()
1853 b43_phy_write(dev, B43_PHY_RFOVERVAL, backup_phy[3]); in b43_calc_loopback_gain()
1854 b43_phy_write(dev, B43_PHY_CRS0, backup_phy[0]); in b43_calc_loopback_gain()
1855 b43_phy_write(dev, B43_PHY_CCKBBANDCFG, backup_phy[1]); in b43_calc_loopback_gain()
1862 static void b43_hardware_pctl_early_init(struct b43_wldev *dev) in b43_hardware_pctl_early_init() argument
1864 struct b43_phy *phy = &dev->phy; in b43_hardware_pctl_early_init()
1866 if (!b43_has_hardware_pctl(dev)) { in b43_hardware_pctl_early_init()
1867 b43_phy_write(dev, 0x047A, 0xC111); in b43_hardware_pctl_early_init()
1871 b43_phy_mask(dev, 0x0036, 0xFEFF); in b43_hardware_pctl_early_init()
1872 b43_phy_write(dev, 0x002F, 0x0202); in b43_hardware_pctl_early_init()
1873 b43_phy_set(dev, 0x047C, 0x0002); in b43_hardware_pctl_early_init()
1874 b43_phy_set(dev, 0x047A, 0xF000); in b43_hardware_pctl_early_init()
1876 b43_phy_maskset(dev, 0x047A, 0xFF0F, 0x0010); in b43_hardware_pctl_early_init()
1877 b43_phy_set(dev, 0x005D, 0x8000); in b43_hardware_pctl_early_init()
1878 b43_phy_maskset(dev, 0x004E, 0xFFC0, 0x0010); in b43_hardware_pctl_early_init()
1879 b43_phy_write(dev, 0x002E, 0xC07F); in b43_hardware_pctl_early_init()
1880 b43_phy_set(dev, 0x0036, 0x0400); in b43_hardware_pctl_early_init()
1882 b43_phy_set(dev, 0x0036, 0x0200); in b43_hardware_pctl_early_init()
1883 b43_phy_set(dev, 0x0036, 0x0400); in b43_hardware_pctl_early_init()
1884 b43_phy_mask(dev, 0x005D, 0x7FFF); in b43_hardware_pctl_early_init()
1885 b43_phy_mask(dev, 0x004F, 0xFFFE); in b43_hardware_pctl_early_init()
1886 b43_phy_maskset(dev, 0x004E, 0xFFC0, 0x0010); in b43_hardware_pctl_early_init()
1887 b43_phy_write(dev, 0x002E, 0xC07F); in b43_hardware_pctl_early_init()
1888 b43_phy_maskset(dev, 0x047A, 0xFF0F, 0x0010); in b43_hardware_pctl_early_init()
1893 static void b43_hardware_pctl_init_gphy(struct b43_wldev *dev) in b43_hardware_pctl_init_gphy() argument
1895 struct b43_phy *phy = &dev->phy; in b43_hardware_pctl_init_gphy()
1898 if (!b43_has_hardware_pctl(dev)) { in b43_hardware_pctl_init_gphy()
1900 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_HWPCTL); in b43_hardware_pctl_init_gphy()
1904 b43_phy_maskset(dev, 0x0036, 0xFFC0, (gphy->tgt_idle_tssi - gphy->cur_idle_tssi)); in b43_hardware_pctl_init_gphy()
1905 b43_phy_maskset(dev, 0x0478, 0xFF00, (gphy->tgt_idle_tssi - gphy->cur_idle_tssi)); in b43_hardware_pctl_init_gphy()
1906 b43_gphy_tssi_power_lt_init(dev); in b43_hardware_pctl_init_gphy()
1907 b43_gphy_gain_lt_init(dev); in b43_hardware_pctl_init_gphy()
1908 b43_phy_mask(dev, 0x0060, 0xFFBF); in b43_hardware_pctl_init_gphy()
1909 b43_phy_write(dev, 0x0014, 0x0000); in b43_hardware_pctl_init_gphy()
1912 b43_phy_set(dev, 0x0478, 0x0800); in b43_hardware_pctl_init_gphy()
1913 b43_phy_mask(dev, 0x0478, 0xFEFF); in b43_hardware_pctl_init_gphy()
1914 b43_phy_mask(dev, 0x0801, 0xFFBF); in b43_hardware_pctl_init_gphy()
1916 b43_gphy_dc_lt_init(dev, 1); in b43_hardware_pctl_init_gphy()
1919 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_HWPCTL); in b43_hardware_pctl_init_gphy()
1923 static void b43_phy_init_pctl(struct b43_wldev *dev) in b43_phy_init_pctl() argument
1925 struct b43_phy *phy = &dev->phy; in b43_phy_init_pctl()
1933 if ((dev->dev->board_vendor == SSB_BOARDVENDOR_BCM) && in b43_phy_init_pctl()
1934 (dev->dev->board_type == SSB_BOARD_BU4306)) in b43_phy_init_pctl()
1937 b43_phy_write(dev, 0x0028, 0x8018); in b43_phy_init_pctl()
1940 b43_write16(dev, B43_MMIO_PHY0, b43_read16(dev, B43_MMIO_PHY0) in b43_phy_init_pctl()
1945 b43_hardware_pctl_early_init(dev); in b43_phy_init_pctl()
1948 b43_radio_maskset(dev, 0x0076, 0x00F7, 0x0084); in b43_phy_init_pctl()
1965 b43_set_txpower_g(dev, &bbatt, &rfatt, 0); in b43_phy_init_pctl()
1967 b43_dummy_transmission(dev, false, true); in b43_phy_init_pctl()
1968 gphy->cur_idle_tssi = b43_phy_read(dev, B43_PHY_ITSSI); in b43_phy_init_pctl()
1972 b43dbg(dev->wl, in b43_phy_init_pctl()
1981 b43_radio_mask(dev, 0x0076, 0xFF7B); in b43_phy_init_pctl()
1983 b43_set_txpower_g(dev, &old_bbatt, in b43_phy_init_pctl()
1987 b43_hardware_pctl_init_gphy(dev); in b43_phy_init_pctl()
1988 b43_shm_clear_tssi(dev); in b43_phy_init_pctl()
1991 static void b43_phy_inita(struct b43_wldev *dev) in b43_phy_inita() argument
1993 struct b43_phy *phy = &dev->phy; in b43_phy_inita()
1998 if (b43_phy_read(dev, B43_PHY_ENCORE) & B43_PHY_ENCORE_EN) in b43_phy_inita()
1999 b43_phy_set(dev, B43_PHY_ENCORE, 0x0010); in b43_phy_inita()
2001 b43_phy_mask(dev, B43_PHY_ENCORE, ~0x1010); in b43_phy_inita()
2004 b43_wa_all(dev); in b43_phy_inita()
2006 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) in b43_phy_inita()
2007 b43_phy_maskset(dev, B43_PHY_OFDM(0x6E), 0xE000, 0x3CF); in b43_phy_inita()
2010 static void b43_phy_initg(struct b43_wldev *dev) in b43_phy_initg() argument
2012 struct b43_phy *phy = &dev->phy; in b43_phy_initg()
2017 b43_phy_initb5(dev); in b43_phy_initg()
2019 b43_phy_initb6(dev); in b43_phy_initg()
2022 b43_phy_inita(dev); in b43_phy_initg()
2025 b43_phy_write(dev, B43_PHY_ANALOGOVER, 0); in b43_phy_initg()
2026 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, 0); in b43_phy_initg()
2029 b43_phy_write(dev, B43_PHY_RFOVER, 0); in b43_phy_initg()
2030 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0); in b43_phy_initg()
2033 b43_phy_write(dev, B43_PHY_RFOVER, 0x400); in b43_phy_initg()
2034 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0); in b43_phy_initg()
2037 tmp = b43_phy_read(dev, B43_PHY_VERSION_OFDM); in b43_phy_initg()
2040 b43_phy_write(dev, B43_PHY_OFDM(0xC2), 0x1816); in b43_phy_initg()
2041 b43_phy_write(dev, B43_PHY_OFDM(0xC3), 0x8006); in b43_phy_initg()
2044 b43_phy_maskset(dev, B43_PHY_OFDM(0xCC), 0x00FF, 0x1F00); in b43_phy_initg()
2048 b43_phy_write(dev, B43_PHY_OFDM(0x7E), 0x78); in b43_phy_initg()
2050 b43_phy_set(dev, B43_PHY_EXTG(0x01), 0x80); in b43_phy_initg()
2051 b43_phy_set(dev, B43_PHY_OFDM(0x3E), 0x4); in b43_phy_initg()
2054 b43_calc_loopback_gain(dev); in b43_phy_initg()
2058 gphy->initval = b43_radio_init2050(dev); in b43_phy_initg()
2060 b43_radio_write16(dev, 0x0078, gphy->initval); in b43_phy_initg()
2062 b43_lo_g_init(dev); in b43_phy_initg()
2064 b43_radio_write16(dev, 0x52, in b43_phy_initg()
2065 (b43_radio_read16(dev, 0x52) & 0xFF00) in b43_phy_initg()
2069 b43_radio_maskset(dev, 0x52, 0xFFF0, gphy->lo_control->tx_bias); in b43_phy_initg()
2072 b43_phy_maskset(dev, B43_PHY_CCK(0x36), 0x0FFF, (gphy->lo_control->tx_bias << 12)); in b43_phy_initg()
2074 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) in b43_phy_initg()
2075 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8075); in b43_phy_initg()
2077 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x807F); in b43_phy_initg()
2079 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x101); in b43_phy_initg()
2081 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x202); in b43_phy_initg()
2083 b43_lo_g_adjust(dev); in b43_phy_initg()
2084 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078); in b43_phy_initg()
2087 if (!(dev->dev->bus_sprom->boardflags_lo & B43_BFL_RSSI)) { in b43_phy_initg()
2094 b43_nrssi_hw_update(dev, 0xFFFF); //FIXME? in b43_phy_initg()
2095 b43_calc_nrssi_threshold(dev); in b43_phy_initg()
2099 b43_calc_nrssi_slope(dev); in b43_phy_initg()
2101 b43_calc_nrssi_threshold(dev); in b43_phy_initg()
2104 b43_phy_write(dev, B43_PHY_EXTG(0x05), 0x3230); in b43_phy_initg()
2105 b43_phy_init_pctl(dev); in b43_phy_initg()
2109 if ((dev->dev->chip_id == 0x4306 in b43_phy_initg()
2110 && dev->dev->chip_pkg == 2) || 0) { in b43_phy_initg()
2111 b43_phy_mask(dev, B43_PHY_CRS0, 0xBFFF); in b43_phy_initg()
2112 b43_phy_mask(dev, B43_PHY_OFDM(0xC3), 0x7FFF); in b43_phy_initg()
2116 void b43_gphy_channel_switch(struct b43_wldev *dev, in b43_gphy_channel_switch() argument
2121 b43_synth_pu_workaround(dev, channel); in b43_gphy_channel_switch()
2123 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel)); in b43_gphy_channel_switch()
2126 if (dev->dev->bus_sprom->country_code == in b43_gphy_channel_switch()
2128 b43_hf_write(dev, in b43_gphy_channel_switch()
2129 b43_hf_read(dev) & ~B43_HF_ACPR); in b43_gphy_channel_switch()
2131 b43_hf_write(dev, in b43_gphy_channel_switch()
2132 b43_hf_read(dev) | B43_HF_ACPR); in b43_gphy_channel_switch()
2133 b43_write16(dev, B43_MMIO_CHANNEL_EXT, in b43_gphy_channel_switch()
2134 b43_read16(dev, B43_MMIO_CHANNEL_EXT) in b43_gphy_channel_switch()
2137 b43_write16(dev, B43_MMIO_CHANNEL_EXT, in b43_gphy_channel_switch()
2138 b43_read16(dev, B43_MMIO_CHANNEL_EXT) in b43_gphy_channel_switch()
2143 static void default_baseband_attenuation(struct b43_wldev *dev, in default_baseband_attenuation() argument
2146 struct b43_phy *phy = &dev->phy; in default_baseband_attenuation()
2154 static void default_radio_attenuation(struct b43_wldev *dev, in default_radio_attenuation() argument
2157 struct b43_bus_dev *bdev = dev->dev; in default_radio_attenuation()
2158 struct b43_phy *phy = &dev->phy; in default_radio_attenuation()
2162 if (dev->dev->board_vendor == SSB_BOARDVENDOR_BCM && in default_radio_attenuation()
2163 dev->dev->board_type == SSB_BOARD_BCM4309G) { in default_radio_attenuation()
2164 if (dev->dev->board_rev < 0x43) { in default_radio_attenuation()
2167 } else if (dev->dev->board_rev < 0x51) { in default_radio_attenuation()
2250 static u16 default_tx_control(struct b43_wldev *dev) in default_tx_control() argument
2252 struct b43_phy *phy = &dev->phy; in default_tx_control()
2265 static u8 b43_gphy_aci_detect(struct b43_wldev *dev, u8 channel) in b43_gphy_aci_detect() argument
2267 struct b43_phy *phy = &dev->phy; in b43_gphy_aci_detect()
2273 saved = b43_phy_read(dev, 0x0403); in b43_gphy_aci_detect()
2274 b43_switch_channel(dev, channel); in b43_gphy_aci_detect()
2275 b43_phy_write(dev, 0x0403, (saved & 0xFFF8) | 5); in b43_gphy_aci_detect()
2277 rssi = b43_phy_read(dev, 0x048A) & 0x3F; in b43_gphy_aci_detect()
2284 temp = (b43_phy_read(dev, 0x047F) >> 8) & 0x3F; in b43_gphy_aci_detect()
2292 b43_phy_write(dev, 0x0403, saved); in b43_gphy_aci_detect()
2297 static u8 b43_gphy_aci_scan(struct b43_wldev *dev) in b43_gphy_aci_scan() argument
2299 struct b43_phy *phy = &dev->phy; in b43_gphy_aci_scan()
2307 b43_phy_lock(dev); in b43_gphy_aci_scan()
2308 b43_radio_lock(dev); in b43_gphy_aci_scan()
2309 b43_phy_mask(dev, 0x0802, 0xFFFC); in b43_gphy_aci_scan()
2310 b43_phy_mask(dev, B43_PHY_G_CRS, 0x7FFF); in b43_gphy_aci_scan()
2311 b43_set_all_gains(dev, 3, 8, 1); in b43_gphy_aci_scan()
2318 ret[i - 1] = b43_gphy_aci_detect(dev, i); in b43_gphy_aci_scan()
2320 b43_switch_channel(dev, channel); in b43_gphy_aci_scan()
2321 b43_phy_maskset(dev, 0x0802, 0xFFFC, 0x0003); in b43_gphy_aci_scan()
2322 b43_phy_mask(dev, 0x0403, 0xFFF8); in b43_gphy_aci_scan()
2323 b43_phy_set(dev, B43_PHY_G_CRS, 0x8000); in b43_gphy_aci_scan()
2324 b43_set_original_gains(dev); in b43_gphy_aci_scan()
2332 b43_radio_unlock(dev); in b43_gphy_aci_scan()
2333 b43_phy_unlock(dev); in b43_gphy_aci_scan()
2367 u8 *b43_generate_dyn_tssi2dbm_tab(struct b43_wldev *dev, in b43_generate_dyn_tssi2dbm_tab() argument
2376 b43err(dev->wl, "Could not allocate memory " in b43_generate_dyn_tssi2dbm_tab()
2383 b43err(dev->wl, "Could not generate " in b43_generate_dyn_tssi2dbm_tab()
2394 static int b43_gphy_init_tssi2dbm_table(struct b43_wldev *dev) in b43_gphy_init_tssi2dbm_table() argument
2396 struct b43_phy *phy = &dev->phy; in b43_gphy_init_tssi2dbm_table()
2400 pab0 = (s16) (dev->dev->bus_sprom->pa0b0); in b43_gphy_init_tssi2dbm_table()
2401 pab1 = (s16) (dev->dev->bus_sprom->pa0b1); in b43_gphy_init_tssi2dbm_table()
2402 pab2 = (s16) (dev->dev->bus_sprom->pa0b2); in b43_gphy_init_tssi2dbm_table()
2404 B43_WARN_ON((dev->dev->chip_id == 0x4301) && in b43_gphy_init_tssi2dbm_table()
2412 if ((s8) dev->dev->bus_sprom->itssi_bg != 0 && in b43_gphy_init_tssi2dbm_table()
2413 (s8) dev->dev->bus_sprom->itssi_bg != -1) { in b43_gphy_init_tssi2dbm_table()
2415 (s8) (dev->dev->bus_sprom->itssi_bg); in b43_gphy_init_tssi2dbm_table()
2418 gphy->tssi2dbm = b43_generate_dyn_tssi2dbm_tab(dev, pab0, in b43_gphy_init_tssi2dbm_table()
2432 static int b43_gphy_op_allocate(struct b43_wldev *dev) in b43_gphy_op_allocate() argument
2443 dev->phy.g = gphy; in b43_gphy_op_allocate()
2452 err = b43_gphy_init_tssi2dbm_table(dev); in b43_gphy_op_allocate()
2466 static void b43_gphy_op_prepare_structs(struct b43_wldev *dev) in b43_gphy_op_prepare_structs() argument
2468 struct b43_phy *phy = &dev->phy; in b43_gphy_op_prepare_structs()
2513 static void b43_gphy_op_free(struct b43_wldev *dev) in b43_gphy_op_free() argument
2515 struct b43_phy *phy = &dev->phy; in b43_gphy_op_free()
2526 dev->phy.g = NULL; in b43_gphy_op_free()
2529 static int b43_gphy_op_prepare_hardware(struct b43_wldev *dev) in b43_gphy_op_prepare_hardware() argument
2531 struct b43_phy *phy = &dev->phy; in b43_gphy_op_prepare_hardware()
2537 default_baseband_attenuation(dev, &gphy->bbatt); in b43_gphy_op_prepare_hardware()
2538 default_radio_attenuation(dev, &gphy->rfatt); in b43_gphy_op_prepare_hardware()
2539 gphy->tx_control = (default_tx_control(dev) << 4); in b43_gphy_op_prepare_hardware()
2540 generate_rfatt_list(dev, &lo->rfatt_list); in b43_gphy_op_prepare_hardware()
2541 generate_bbatt_list(dev, &lo->bbatt_list); in b43_gphy_op_prepare_hardware()
2544 b43_read32(dev, B43_MMIO_MACCTL); in b43_gphy_op_prepare_hardware()
2550 b43_wireless_core_reset(dev, 0); in b43_gphy_op_prepare_hardware()
2551 b43_phy_initg(dev); in b43_gphy_op_prepare_hardware()
2553 b43_wireless_core_reset(dev, 1); in b43_gphy_op_prepare_hardware()
2559 static int b43_gphy_op_init(struct b43_wldev *dev) in b43_gphy_op_init() argument
2561 b43_phy_initg(dev); in b43_gphy_op_init()
2566 static void b43_gphy_op_exit(struct b43_wldev *dev) in b43_gphy_op_exit() argument
2568 b43_lo_g_cleanup(dev); in b43_gphy_op_exit()
2571 static u16 b43_gphy_op_read(struct b43_wldev *dev, u16 reg) in b43_gphy_op_read() argument
2573 b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); in b43_gphy_op_read()
2574 return b43_read16(dev, B43_MMIO_PHY_DATA); in b43_gphy_op_read()
2577 static void b43_gphy_op_write(struct b43_wldev *dev, u16 reg, u16 value) in b43_gphy_op_write() argument
2579 b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); in b43_gphy_op_write()
2580 b43_write16(dev, B43_MMIO_PHY_DATA, value); in b43_gphy_op_write()
2583 static u16 b43_gphy_op_radio_read(struct b43_wldev *dev, u16 reg) in b43_gphy_op_radio_read() argument
2590 b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); in b43_gphy_op_radio_read()
2591 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); in b43_gphy_op_radio_read()
2594 static void b43_gphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value) in b43_gphy_op_radio_write() argument
2599 b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); in b43_gphy_op_radio_write()
2600 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value); in b43_gphy_op_radio_write()
2603 static bool b43_gphy_op_supports_hwpctl(struct b43_wldev *dev) in b43_gphy_op_supports_hwpctl() argument
2605 return (dev->phy.rev >= 6); in b43_gphy_op_supports_hwpctl()
2608 static void b43_gphy_op_software_rfkill(struct b43_wldev *dev, in b43_gphy_op_software_rfkill() argument
2611 struct b43_phy *phy = &dev->phy; in b43_gphy_op_software_rfkill()
2622 b43_phy_write(dev, 0x0015, 0x8000); in b43_gphy_op_software_rfkill()
2623 b43_phy_write(dev, 0x0015, 0xCC00); in b43_gphy_op_software_rfkill()
2624 b43_phy_write(dev, 0x0015, (phy->gmode ? 0x00C0 : 0x0000)); in b43_gphy_op_software_rfkill()
2627 b43_phy_write(dev, B43_PHY_RFOVER, in b43_gphy_op_software_rfkill()
2629 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_gphy_op_software_rfkill()
2634 b43_gphy_channel_switch(dev, 6, 1); in b43_gphy_op_software_rfkill()
2635 b43_gphy_channel_switch(dev, channel, 0); in b43_gphy_op_software_rfkill()
2640 rfover = b43_phy_read(dev, B43_PHY_RFOVER); in b43_gphy_op_software_rfkill()
2641 rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL); in b43_gphy_op_software_rfkill()
2645 b43_phy_write(dev, B43_PHY_RFOVER, rfover | 0x008C); in b43_gphy_op_software_rfkill()
2646 b43_phy_write(dev, B43_PHY_RFOVERVAL, rfoverval & 0xFF73); in b43_gphy_op_software_rfkill()
2650 static int b43_gphy_op_switch_channel(struct b43_wldev *dev, in b43_gphy_op_switch_channel() argument
2655 b43_gphy_channel_switch(dev, new_channel, 0); in b43_gphy_op_switch_channel()
2660 static unsigned int b43_gphy_op_get_default_chan(struct b43_wldev *dev) in b43_gphy_op_get_default_chan() argument
2665 static void b43_gphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna) in b43_gphy_op_set_rx_antenna() argument
2667 struct b43_phy *phy = &dev->phy; in b43_gphy_op_set_rx_antenna()
2674 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ANTDIVHELP); in b43_gphy_op_set_rx_antenna()
2676 b43_phy_maskset(dev, B43_PHY_BBANDCFG, ~B43_PHY_BBANDCFG_RXANT, in b43_gphy_op_set_rx_antenna()
2681 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL); in b43_gphy_op_set_rx_antenna()
2686 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp); in b43_gphy_op_set_rx_antenna()
2689 tmp = b43_phy_read(dev, B43_PHY_ANTWRSETT); in b43_gphy_op_set_rx_antenna()
2694 b43_phy_write(dev, B43_PHY_ANTWRSETT, tmp); in b43_gphy_op_set_rx_antenna()
2697 b43_phy_set(dev, B43_PHY_ANTWRSETT, B43_PHY_ANTWRSETT_ARXDIV); in b43_gphy_op_set_rx_antenna()
2699 b43_phy_mask(dev, B43_PHY_ANTWRSETT, in b43_gphy_op_set_rx_antenna()
2704 b43_phy_set(dev, B43_PHY_OFDM61, B43_PHY_OFDM61_10); in b43_gphy_op_set_rx_antenna()
2705 b43_phy_maskset(dev, B43_PHY_DIVSRCHGAINBACK, 0xFF00, 0x15); in b43_gphy_op_set_rx_antenna()
2708 b43_phy_write(dev, B43_PHY_ADIVRELATED, 8); in b43_gphy_op_set_rx_antenna()
2710 b43_phy_maskset(dev, B43_PHY_ADIVRELATED, 0xFF00, 8); in b43_gphy_op_set_rx_antenna()
2713 b43_phy_write(dev, B43_PHY_OFDM9B, 0xDC); in b43_gphy_op_set_rx_antenna()
2715 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ANTDIVHELP); in b43_gphy_op_set_rx_antenna()
2718 static int b43_gphy_op_interf_mitigation(struct b43_wldev *dev, in b43_gphy_op_interf_mitigation() argument
2721 struct b43_phy *phy = &dev->phy; in b43_gphy_op_interf_mitigation()
2750 b43_radio_interference_mitigation_disable(dev, currentmode); in b43_gphy_op_interf_mitigation()
2756 b43_radio_interference_mitigation_enable(dev, mode); in b43_gphy_op_interf_mitigation()
2765 static s8 b43_gphy_estimate_power_out(struct b43_wldev *dev, s8 tssi) in b43_gphy_estimate_power_out() argument
2767 struct b43_phy_g *gphy = dev->phy.g; in b43_gphy_estimate_power_out()
2778 static void b43_put_attenuation_into_ranges(struct b43_wldev *dev, in b43_put_attenuation_into_ranges() argument
2783 struct b43_txpower_lo_control *lo = dev->phy.g->lo_control; in b43_put_attenuation_into_ranges()
2831 static void b43_gphy_op_adjust_txpower(struct b43_wldev *dev) in b43_gphy_op_adjust_txpower() argument
2833 struct b43_phy *phy = &dev->phy; in b43_gphy_op_adjust_txpower()
2838 b43_mac_suspend(dev); in b43_gphy_op_adjust_txpower()
2846 b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt); in b43_gphy_op_adjust_txpower()
2856 } else if (dev->dev->bus_sprom-> in b43_gphy_op_adjust_txpower()
2875 b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt); in b43_gphy_op_adjust_txpower()
2879 if (b43_debug(dev, B43_DBG_XMITPOWER)) in b43_gphy_op_adjust_txpower()
2880 b43dbg(dev->wl, "Adjusting TX power\n"); in b43_gphy_op_adjust_txpower()
2883 b43_phy_lock(dev); in b43_gphy_op_adjust_txpower()
2884 b43_radio_lock(dev); in b43_gphy_op_adjust_txpower()
2885 b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, in b43_gphy_op_adjust_txpower()
2887 b43_radio_unlock(dev); in b43_gphy_op_adjust_txpower()
2888 b43_phy_unlock(dev); in b43_gphy_op_adjust_txpower()
2890 b43_mac_enable(dev); in b43_gphy_op_adjust_txpower()
2893 static enum b43_txpwr_result b43_gphy_op_recalc_txpower(struct b43_wldev *dev, in b43_gphy_op_recalc_txpower() argument
2896 struct b43_phy *phy = &dev->phy; in b43_gphy_op_recalc_txpower()
2905 cck_result = b43_phy_shm_tssi_read(dev, B43_SHM_SH_TSSI_CCK); in b43_gphy_op_recalc_txpower()
2906 ofdm_result = b43_phy_shm_tssi_read(dev, B43_SHM_SH_TSSI_OFDM_G); in b43_gphy_op_recalc_txpower()
2927 estimated_pwr = b43_gphy_estimate_power_out(dev, average_tssi); in b43_gphy_op_recalc_txpower()
2930 max_pwr = dev->dev->bus_sprom->maxpwr_bg; in b43_gphy_op_recalc_txpower()
2931 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) in b43_gphy_op_recalc_txpower()
2934 b43warn(dev->wl, in b43_gphy_op_recalc_txpower()
2937 dev->dev->bus_sprom->maxpwr_bg = max_pwr; in b43_gphy_op_recalc_txpower()
2947 if (b43_debug(dev, B43_DBG_XMITPOWER)) { in b43_gphy_op_recalc_txpower()
2948 b43dbg(dev->wl, in b43_gphy_op_recalc_txpower()
2976 if (b43_debug(dev, B43_DBG_XMITPOWER)) { in b43_gphy_op_recalc_txpower()
2978 b43dbg(dev->wl, in b43_gphy_op_recalc_txpower()
3001 static void b43_gphy_op_pwork_15sec(struct b43_wldev *dev) in b43_gphy_op_pwork_15sec() argument
3003 struct b43_phy *phy = &dev->phy; in b43_gphy_op_pwork_15sec()
3006 b43_mac_suspend(dev); in b43_gphy_op_pwork_15sec()
3011 phy->ops->interf_mitigation(dev, in b43_gphy_op_pwork_15sec()
3015 if (/*(aci_average > 1000) &&*/ !b43_gphy_aci_scan(dev)) in b43_gphy_op_pwork_15sec()
3016 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE); in b43_gphy_op_pwork_15sec()
3022 b43_lo_g_maintenance_work(dev); in b43_gphy_op_pwork_15sec()
3023 b43_mac_enable(dev); in b43_gphy_op_pwork_15sec()
3026 static void b43_gphy_op_pwork_60sec(struct b43_wldev *dev) in b43_gphy_op_pwork_60sec() argument
3028 struct b43_phy *phy = &dev->phy; in b43_gphy_op_pwork_60sec()
3030 if (!(dev->dev->bus_sprom->boardflags_lo & B43_BFL_RSSI)) in b43_gphy_op_pwork_60sec()
3033 b43_mac_suspend(dev); in b43_gphy_op_pwork_60sec()
3034 b43_calc_nrssi_slope(dev); in b43_gphy_op_pwork_60sec()
3040 b43_switch_channel(dev, 1); in b43_gphy_op_pwork_60sec()
3042 b43_switch_channel(dev, 13); in b43_gphy_op_pwork_60sec()
3043 b43_switch_channel(dev, old_chan); in b43_gphy_op_pwork_60sec()
3045 b43_mac_enable(dev); in b43_gphy_op_pwork_60sec()