110 	B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));  in op32_fill_descriptor()
202 	B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));  in op64_fill_descriptor()
277 	B43_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));  in next_slot()
285 	B43_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));  in prev_slot()
317 	B43_WARN_ON(!ring->tx);  in request_slot()
318 	B43_WARN_ON(ring->stopped);  in request_slot()
319 	B43_WARN_ON(free_slots(ring) == 0);  in request_slot()
350 		B43_WARN_ON(!(controller_idx >= 0 &&  in b43_dmacontroller_base()
354 	B43_WARN_ON(!(controller_idx >= 0 &&  in b43_dmacontroller_base()
393 	B43_WARN_ON(ring->tx);  in sync_descbuffer_for_cpu()
402 	B43_WARN_ON(ring->tx);  in sync_descbuffer_for_device()
600 	B43_WARN_ON(ring->rx_buffersize < ring->frameoffset + sizeof(struct b43_plcp_hdr6) + 2);  in b43_poison_rx_buffer()
612 	B43_WARN_ON(ring->tx);  in setup_rx_descbuffer()
799 			B43_WARN_ON(!ring->tx);  in free_all_descbuffers()
852 	B43_WARN_ON(1);  in dma_mask_to_engine_type()
907 			B43_WARN_ON(1);  in b43_setup_dmaring()
1176 	B43_WARN_ON(dev->dev->core_rev < 5);  in b43_dma_init()
1211 	B43_WARN_ON(slot & ~0x0FFF);  in generate_cookie()
1381 			B43_WARN_ON(1);  in select_ring_by_priority()
1422 	B43_WARN_ON(!ring->tx);  in b43_dma_tx()
1492 	B43_WARN_ON(!ring->tx);  in b43_dma_handle_txstatus()
1536 		B43_WARN_ON(slot < 0 || slot >= ring->nr_slots);  in b43_dma_handle_txstatus()
1626 		B43_WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME);  in b43_dma_handle_txstatus()
1734 	B43_WARN_ON(ring->tx);  in b43_dma_handle_rx_overflow()
1755 	B43_WARN_ON(ring->tx);  in b43_dma_rx()
1757 	B43_WARN_ON(!(current_slot >= 0 && current_slot < ring->nr_slots));  in b43_dma_rx()
1771 	B43_WARN_ON(!ring->tx);  in b43_dma_tx_suspend_ring()
1777 	B43_WARN_ON(!ring->tx);  in b43_dma_tx_resume_ring()