Lines Matching refs:wil
86 static void wil6210_mask_irq_tx(struct wil6210_priv *wil) in wil6210_mask_irq_tx() argument
88 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, IMS), in wil6210_mask_irq_tx()
92 static void wil6210_mask_irq_tx_edma(struct wil6210_priv *wil) in wil6210_mask_irq_tx_edma() argument
94 wil_w(wil, RGF_INT_GEN_TX_ICR + offsetof(struct RGF_ICR, IMS), in wil6210_mask_irq_tx_edma()
98 static void wil6210_mask_irq_rx(struct wil6210_priv *wil) in wil6210_mask_irq_rx() argument
100 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, IMS), in wil6210_mask_irq_rx()
104 static void wil6210_mask_irq_rx_edma(struct wil6210_priv *wil) in wil6210_mask_irq_rx_edma() argument
106 wil_w(wil, RGF_INT_GEN_RX_ICR + offsetof(struct RGF_ICR, IMS), in wil6210_mask_irq_rx_edma()
110 static void wil6210_mask_irq_misc(struct wil6210_priv *wil, bool mask_halp) in wil6210_mask_irq_misc() argument
112 wil_dbg_irq(wil, "mask_irq_misc: mask_halp(%s)\n", in wil6210_mask_irq_misc()
115 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS), in wil6210_mask_irq_misc()
119 void wil6210_mask_halp(struct wil6210_priv *wil) in wil6210_mask_halp() argument
121 wil_dbg_irq(wil, "mask_halp\n"); in wil6210_mask_halp()
123 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS), in wil6210_mask_halp()
127 static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil) in wil6210_mask_irq_pseudo() argument
129 wil_dbg_irq(wil, "mask_irq_pseudo\n"); in wil6210_mask_irq_pseudo()
131 wil_w(wil, RGF_DMA_PSEUDO_CAUSE_MASK_SW, WIL6210_IRQ_DISABLE); in wil6210_mask_irq_pseudo()
133 clear_bit(wil_status_irqen, wil->status); in wil6210_mask_irq_pseudo()
136 void wil6210_unmask_irq_tx(struct wil6210_priv *wil) in wil6210_unmask_irq_tx() argument
138 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, IMC), in wil6210_unmask_irq_tx()
142 void wil6210_unmask_irq_tx_edma(struct wil6210_priv *wil) in wil6210_unmask_irq_tx_edma() argument
144 wil_w(wil, RGF_INT_GEN_TX_ICR + offsetof(struct RGF_ICR, IMC), in wil6210_unmask_irq_tx_edma()
148 void wil6210_unmask_irq_rx(struct wil6210_priv *wil) in wil6210_unmask_irq_rx() argument
150 bool unmask_rx_htrsh = atomic_read(&wil->connected_vifs) > 0; in wil6210_unmask_irq_rx()
152 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, IMC), in wil6210_unmask_irq_rx()
156 void wil6210_unmask_irq_rx_edma(struct wil6210_priv *wil) in wil6210_unmask_irq_rx_edma() argument
158 wil_w(wil, RGF_INT_GEN_RX_ICR + offsetof(struct RGF_ICR, IMC), in wil6210_unmask_irq_rx_edma()
162 static void wil6210_unmask_irq_misc(struct wil6210_priv *wil, bool unmask_halp) in wil6210_unmask_irq_misc() argument
164 wil_dbg_irq(wil, "unmask_irq_misc: unmask_halp(%s)\n", in wil6210_unmask_irq_misc()
167 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC), in wil6210_unmask_irq_misc()
171 static void wil6210_unmask_halp(struct wil6210_priv *wil) in wil6210_unmask_halp() argument
173 wil_dbg_irq(wil, "unmask_halp\n"); in wil6210_unmask_halp()
175 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC), in wil6210_unmask_halp()
179 static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil) in wil6210_unmask_irq_pseudo() argument
181 wil_dbg_irq(wil, "unmask_irq_pseudo\n"); in wil6210_unmask_irq_pseudo()
183 set_bit(wil_status_irqen, wil->status); in wil6210_unmask_irq_pseudo()
185 wil_w(wil, RGF_DMA_PSEUDO_CAUSE_MASK_SW, WIL6210_IRQ_PSEUDO_MASK); in wil6210_unmask_irq_pseudo()
188 void wil_mask_irq(struct wil6210_priv *wil) in wil_mask_irq() argument
190 wil_dbg_irq(wil, "mask_irq\n"); in wil_mask_irq()
192 wil6210_mask_irq_tx(wil); in wil_mask_irq()
193 wil6210_mask_irq_tx_edma(wil); in wil_mask_irq()
194 wil6210_mask_irq_rx(wil); in wil_mask_irq()
195 wil6210_mask_irq_rx_edma(wil); in wil_mask_irq()
196 wil6210_mask_irq_misc(wil, true); in wil_mask_irq()
197 wil6210_mask_irq_pseudo(wil); in wil_mask_irq()
200 void wil_unmask_irq(struct wil6210_priv *wil) in wil_unmask_irq() argument
202 wil_dbg_irq(wil, "unmask_irq\n"); in wil_unmask_irq()
204 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, ICC), in wil_unmask_irq()
206 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, ICC), in wil_unmask_irq()
208 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICC), in wil_unmask_irq()
210 wil_w(wil, RGF_INT_GEN_TX_ICR + offsetof(struct RGF_ICR, ICC), in wil_unmask_irq()
212 wil_w(wil, RGF_INT_GEN_RX_ICR + offsetof(struct RGF_ICR, ICC), in wil_unmask_irq()
215 wil6210_unmask_irq_pseudo(wil); in wil_unmask_irq()
216 if (wil->use_enhanced_dma_hw) { in wil_unmask_irq()
217 wil6210_unmask_irq_tx_edma(wil); in wil_unmask_irq()
218 wil6210_unmask_irq_rx_edma(wil); in wil_unmask_irq()
220 wil6210_unmask_irq_tx(wil); in wil_unmask_irq()
221 wil6210_unmask_irq_rx(wil); in wil_unmask_irq()
223 wil6210_unmask_irq_misc(wil, true); in wil_unmask_irq()
226 void wil_configure_interrupt_moderation_edma(struct wil6210_priv *wil) in wil_configure_interrupt_moderation_edma() argument
230 wil_s(wil, RGF_INT_GEN_IDLE_TIME_LIMIT, WIL_EDMA_IDLE_TIME_LIMIT_USEC); in wil_configure_interrupt_moderation_edma()
232 wil_s(wil, RGF_INT_GEN_TIME_UNIT_LIMIT, WIL_EDMA_TIME_UNIT_CLK_CYCLES); in wil_configure_interrupt_moderation_edma()
235 moderation = wil->rx_max_burst_duration | in wil_configure_interrupt_moderation_edma()
237 wil_w(wil, RGF_INT_CTRL_INT_GEN_CFG_0, moderation); in wil_configure_interrupt_moderation_edma()
238 wil_w(wil, RGF_INT_CTRL_INT_GEN_CFG_1, moderation); in wil_configure_interrupt_moderation_edma()
243 wil_c(wil, RGF_INT_COUNT_ON_SPECIAL_EVT, 0x1FE); in wil_configure_interrupt_moderation_edma()
244 wil_s(wil, RGF_INT_COUNT_ON_SPECIAL_EVT, 0x1); in wil_configure_interrupt_moderation_edma()
247 void wil_configure_interrupt_moderation(struct wil6210_priv *wil) in wil_configure_interrupt_moderation() argument
249 struct wireless_dev *wdev = wil->main_ndev->ieee80211_ptr; in wil_configure_interrupt_moderation()
251 wil_dbg_irq(wil, "configure_interrupt_moderation\n"); in wil_configure_interrupt_moderation()
260 wil_w(wil, RGF_DMA_ITR_TX_CNT_CTL, BIT_DMA_ITR_TX_CNT_CTL_CLR); in wil_configure_interrupt_moderation()
261 wil_w(wil, RGF_DMA_ITR_TX_CNT_TRSH, wil->tx_max_burst_duration); in wil_configure_interrupt_moderation()
262 wil_info(wil, "set ITR_TX_CNT_TRSH = %d usec\n", in wil_configure_interrupt_moderation()
263 wil->tx_max_burst_duration); in wil_configure_interrupt_moderation()
265 wil_w(wil, RGF_DMA_ITR_TX_CNT_CTL, in wil_configure_interrupt_moderation()
269 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR); in wil_configure_interrupt_moderation()
270 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_TRSH, wil->tx_interframe_timeout); in wil_configure_interrupt_moderation()
271 wil_info(wil, "set ITR_TX_IDL_CNT_TRSH = %d usec\n", in wil_configure_interrupt_moderation()
272 wil->tx_interframe_timeout); in wil_configure_interrupt_moderation()
274 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_EN | in wil_configure_interrupt_moderation()
278 wil_w(wil, RGF_DMA_ITR_RX_CNT_CTL, BIT_DMA_ITR_RX_CNT_CTL_CLR); in wil_configure_interrupt_moderation()
279 wil_w(wil, RGF_DMA_ITR_RX_CNT_TRSH, wil->rx_max_burst_duration); in wil_configure_interrupt_moderation()
280 wil_info(wil, "set ITR_RX_CNT_TRSH = %d usec\n", in wil_configure_interrupt_moderation()
281 wil->rx_max_burst_duration); in wil_configure_interrupt_moderation()
283 wil_w(wil, RGF_DMA_ITR_RX_CNT_CTL, in wil_configure_interrupt_moderation()
287 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR); in wil_configure_interrupt_moderation()
288 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_TRSH, wil->rx_interframe_timeout); in wil_configure_interrupt_moderation()
289 wil_info(wil, "set ITR_RX_IDL_CNT_TRSH = %d usec\n", in wil_configure_interrupt_moderation()
290 wil->rx_interframe_timeout); in wil_configure_interrupt_moderation()
292 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_EN | in wil_configure_interrupt_moderation()
298 struct wil6210_priv *wil = cookie; in wil6210_irq_rx() local
299 u32 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_rx()
305 wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr); in wil6210_irq_rx()
308 wil_err_ratelimited(wil, "spurious IRQ: RX\n"); in wil6210_irq_rx()
312 wil6210_mask_irq_rx(wil); in wil6210_irq_rx()
322 wil_dbg_irq(wil, "RX done / RX_HTRSH received, ISR (0x%x)\n", in wil6210_irq_rx()
327 if (likely(test_bit(wil_status_fwready, wil->status))) { in wil6210_irq_rx()
328 if (likely(test_bit(wil_status_napi_en, wil->status))) { in wil6210_irq_rx()
329 wil_dbg_txrx(wil, "NAPI(Rx) schedule\n"); in wil6210_irq_rx()
331 napi_schedule(&wil->napi_rx); in wil6210_irq_rx()
334 wil, in wil6210_irq_rx()
338 wil_err_ratelimited(wil, "Got Rx interrupt while in reset\n"); in wil6210_irq_rx()
343 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr); in wil6210_irq_rx()
347 atomic_inc(&wil->isr_count_rx); in wil6210_irq_rx()
350 wil6210_unmask_irq_rx(wil); in wil6210_irq_rx()
357 struct wil6210_priv *wil = cookie; in wil6210_irq_rx_edma() local
358 u32 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_rx_edma()
364 wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr); in wil6210_irq_rx_edma()
367 wil_err(wil, "spurious IRQ: RX\n"); in wil6210_irq_rx_edma()
371 wil6210_mask_irq_rx_edma(wil); in wil6210_irq_rx_edma()
374 wil_dbg_irq(wil, "RX status ring\n"); in wil6210_irq_rx_edma()
376 if (likely(test_bit(wil_status_fwready, wil->status))) { in wil6210_irq_rx_edma()
377 if (likely(test_bit(wil_status_napi_en, wil->status))) { in wil6210_irq_rx_edma()
378 wil_dbg_txrx(wil, "NAPI(Rx) schedule\n"); in wil6210_irq_rx_edma()
380 napi_schedule(&wil->napi_rx); in wil6210_irq_rx_edma()
382 wil_err(wil, in wil6210_irq_rx_edma()
386 wil_err(wil, "Got Rx interrupt while in reset\n"); in wil6210_irq_rx_edma()
391 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr); in wil6210_irq_rx_edma()
395 atomic_inc(&wil->isr_count_rx); in wil6210_irq_rx_edma()
398 wil6210_unmask_irq_rx_edma(wil); in wil6210_irq_rx_edma()
405 struct wil6210_priv *wil = cookie; in wil6210_irq_tx_edma() local
406 u32 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_tx_edma()
412 wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr); in wil6210_irq_tx_edma()
415 wil_err(wil, "spurious IRQ: TX\n"); in wil6210_irq_tx_edma()
419 wil6210_mask_irq_tx_edma(wil); in wil6210_irq_tx_edma()
422 wil_dbg_irq(wil, "TX status ring\n"); in wil6210_irq_tx_edma()
424 if (likely(test_bit(wil_status_fwready, wil->status))) { in wil6210_irq_tx_edma()
425 wil_dbg_txrx(wil, "NAPI(Tx) schedule\n"); in wil6210_irq_tx_edma()
427 napi_schedule(&wil->napi_tx); in wil6210_irq_tx_edma()
429 wil_err(wil, "Got Tx status ring IRQ while in reset\n"); in wil6210_irq_tx_edma()
434 wil_err(wil, "un-handled TX ISR bits 0x%08x\n", isr); in wil6210_irq_tx_edma()
438 atomic_inc(&wil->isr_count_tx); in wil6210_irq_tx_edma()
441 wil6210_unmask_irq_tx_edma(wil); in wil6210_irq_tx_edma()
448 struct wil6210_priv *wil = cookie; in wil6210_irq_tx() local
449 u32 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_tx()
455 wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr); in wil6210_irq_tx()
458 wil_err_ratelimited(wil, "spurious IRQ: TX\n"); in wil6210_irq_tx()
462 wil6210_mask_irq_tx(wil); in wil6210_irq_tx()
465 wil_dbg_irq(wil, "TX done\n"); in wil6210_irq_tx()
469 if (likely(test_bit(wil_status_fwready, wil->status))) { in wil6210_irq_tx()
470 wil_dbg_txrx(wil, "NAPI(Tx) schedule\n"); in wil6210_irq_tx()
472 napi_schedule(&wil->napi_tx); in wil6210_irq_tx()
474 wil_err_ratelimited(wil, "Got Tx interrupt while in reset\n"); in wil6210_irq_tx()
479 wil_err_ratelimited(wil, "un-handled TX ISR bits 0x%08x\n", in wil6210_irq_tx()
484 atomic_inc(&wil->isr_count_tx); in wil6210_irq_tx()
487 wil6210_unmask_irq_tx(wil); in wil6210_irq_tx()
492 static void wil_notify_fw_error(struct wil6210_priv *wil) in wil_notify_fw_error() argument
494 struct device *dev = &wil->main_ndev->dev; in wil_notify_fw_error()
500 wil_err(wil, "Notify about firmware error\n"); in wil_notify_fw_error()
504 static void wil_cache_mbox_regs(struct wil6210_priv *wil) in wil_cache_mbox_regs() argument
507 wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX, in wil_cache_mbox_regs()
509 wil_mbox_ring_le2cpus(&wil->mbox_ctl.rx); in wil_cache_mbox_regs()
510 wil_mbox_ring_le2cpus(&wil->mbox_ctl.tx); in wil_cache_mbox_regs()
513 static bool wil_validate_mbox_regs(struct wil6210_priv *wil) in wil_validate_mbox_regs() argument
518 if (wil->mbox_ctl.rx.entry_size < min_size) { in wil_validate_mbox_regs()
519 wil_err(wil, "rx mbox entry too small (%d)\n", in wil_validate_mbox_regs()
520 wil->mbox_ctl.rx.entry_size); in wil_validate_mbox_regs()
523 if (wil->mbox_ctl.tx.entry_size < min_size) { in wil_validate_mbox_regs()
524 wil_err(wil, "tx mbox entry too small (%d)\n", in wil_validate_mbox_regs()
525 wil->mbox_ctl.tx.entry_size); in wil_validate_mbox_regs()
534 struct wil6210_priv *wil = cookie; in wil6210_irq_misc() local
535 u32 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_misc()
540 wil_dbg_irq(wil, "ISR MISC 0x%08x\n", isr); in wil6210_irq_misc()
543 wil_err(wil, "spurious IRQ: MISC\n"); in wil6210_irq_misc()
547 wil6210_mask_irq_misc(wil, false); in wil6210_irq_misc()
550 u32 fw_assert_code = wil_r(wil, wil->rgf_fw_assert_code_addr); in wil6210_irq_misc()
552 wil_r(wil, wil->rgf_ucode_assert_code_addr); in wil6210_irq_misc()
554 wil_err(wil, in wil6210_irq_misc()
557 clear_bit(wil_status_fwready, wil->status); in wil6210_irq_misc()
566 wil_dbg_irq(wil, "IRQ: FW ready\n"); in wil6210_irq_misc()
567 wil_cache_mbox_regs(wil); in wil6210_irq_misc()
568 if (wil_validate_mbox_regs(wil)) in wil6210_irq_misc()
569 set_bit(wil_status_mbox_ready, wil->status); in wil6210_irq_misc()
578 wil_dbg_irq(wil, "irq_misc: HALP IRQ invoked\n"); in wil6210_irq_misc()
579 wil6210_mask_halp(wil); in wil6210_irq_misc()
581 complete(&wil->halp.comp); in wil6210_irq_misc()
584 wil->isr_misc = isr; in wil6210_irq_misc()
589 wil6210_unmask_irq_misc(wil, false); in wil6210_irq_misc()
596 struct wil6210_priv *wil = cookie; in wil6210_irq_misc_thread() local
597 u32 isr = wil->isr_misc; in wil6210_irq_misc_thread()
600 wil_dbg_irq(wil, "Thread ISR MISC 0x%08x\n", isr); in wil6210_irq_misc_thread()
603 wil->recovery_state = fw_recovery_pending; in wil6210_irq_misc_thread()
604 wil_fw_core_dump(wil); in wil6210_irq_misc_thread()
605 wil_notify_fw_error(wil); in wil6210_irq_misc_thread()
607 if (wil->platform_ops.notify) { in wil6210_irq_misc_thread()
608 wil_err(wil, "notify platform driver about FW crash"); in wil6210_irq_misc_thread()
609 wil->platform_ops.notify(wil->platform_handle, in wil6210_irq_misc_thread()
612 wil_fw_error_recovery(wil); in wil6210_irq_misc_thread()
616 wil_dbg_irq(wil, "MBOX event\n"); in wil6210_irq_misc_thread()
617 wmi_recv_cmd(wil); in wil6210_irq_misc_thread()
622 wil_dbg_irq(wil, "un-handled MISC ISR bits 0x%08x\n", isr); in wil6210_irq_misc_thread()
624 wil->isr_misc = 0; in wil6210_irq_misc_thread()
626 wil6210_unmask_irq_misc(wil, false); in wil6210_irq_misc_thread()
631 if (wil->n_msi == 3 && wil->suspend_resp_rcvd) { in wil6210_irq_misc_thread()
632 wil_dbg_irq(wil, "set suspend_resp_comp to true\n"); in wil6210_irq_misc_thread()
633 wil->suspend_resp_comp = true; in wil6210_irq_misc_thread()
634 wake_up_interruptible(&wil->wq); in wil6210_irq_misc_thread()
645 struct wil6210_priv *wil = cookie; in wil6210_thread_irq() local
647 wil_dbg_irq(wil, "Thread IRQ\n"); in wil6210_thread_irq()
649 if (wil->isr_misc) in wil6210_thread_irq()
652 wil6210_unmask_irq_pseudo(wil); in wil6210_thread_irq()
654 if (wil->suspend_resp_rcvd) { in wil6210_thread_irq()
655 wil_dbg_irq(wil, "set suspend_resp_comp to true\n"); in wil6210_thread_irq()
656 wil->suspend_resp_comp = true; in wil6210_thread_irq()
657 wake_up_interruptible(&wil->wq); in wil6210_thread_irq()
669 static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause) in wil6210_debug_irq_mask() argument
675 if (!test_bit(wil_status_irqen, wil->status)) { in wil6210_debug_irq_mask()
676 if (wil->use_enhanced_dma_hw) { in wil6210_debug_irq_mask()
677 icm_rx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
680 icr_rx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
683 imv_rx = wil_r(wil, RGF_INT_GEN_RX_ICR + in wil6210_debug_irq_mask()
685 icm_tx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
688 icr_tx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
691 imv_tx = wil_r(wil, RGF_INT_GEN_TX_ICR + in wil6210_debug_irq_mask()
694 icm_rx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
697 icr_rx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
700 imv_rx = wil_r(wil, RGF_DMA_EP_RX_ICR + in wil6210_debug_irq_mask()
702 icm_tx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
705 icr_tx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
708 imv_tx = wil_r(wil, RGF_DMA_EP_TX_ICR + in wil6210_debug_irq_mask()
711 icm_misc = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
714 icr_misc = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
717 imv_misc = wil_r(wil, RGF_DMA_EP_MISC_ICR + in wil6210_debug_irq_mask()
726 wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n" in wil6210_debug_irq_mask()
744 struct wil6210_priv *wil = cookie; in wil6210_hardirq() local
745 u32 pseudo_cause = wil_r(wil, RGF_DMA_PSEUDO_CAUSE); in wil6210_hardirq()
754 if (unlikely(wil6210_debug_irq_mask(wil, pseudo_cause))) in wil6210_hardirq()
758 wil_dbg_irq(wil, "Pseudo IRQ 0x%08x\n", pseudo_cause); in wil6210_hardirq()
760 wil6210_mask_irq_pseudo(wil); in wil6210_hardirq()
776 (wil->txrx_ops.irq_rx(irq, cookie) == IRQ_WAKE_THREAD)) in wil6210_hardirq()
780 (wil->txrx_ops.irq_tx(irq, cookie) == IRQ_WAKE_THREAD)) in wil6210_hardirq()
789 wil6210_unmask_irq_pseudo(wil); in wil6210_hardirq()
794 static int wil6210_request_3msi(struct wil6210_priv *wil, int irq) in wil6210_request_3msi() argument
803 rc = request_irq(irq, wil->txrx_ops.irq_tx, IRQF_SHARED, in wil6210_request_3msi()
804 WIL_NAME "_tx", wil); in wil6210_request_3msi()
808 rc = request_irq(irq + 1, wil->txrx_ops.irq_rx, IRQF_SHARED, in wil6210_request_3msi()
809 WIL_NAME "_rx", wil); in wil6210_request_3msi()
815 IRQF_SHARED, WIL_NAME "_misc", wil); in wil6210_request_3msi()
821 free_irq(irq + 1, wil); in wil6210_request_3msi()
823 free_irq(irq, wil); in wil6210_request_3msi()
836 void wil6210_clear_irq(struct wil6210_priv *wil) in wil6210_clear_irq() argument
838 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) + in wil6210_clear_irq()
840 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) + in wil6210_clear_irq()
842 wil_clear32(wil->csr + HOSTADDR(RGF_INT_GEN_RX_ICR) + in wil6210_clear_irq()
844 wil_clear32(wil->csr + HOSTADDR(RGF_INT_GEN_TX_ICR) + in wil6210_clear_irq()
846 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) + in wil6210_clear_irq()
851 void wil6210_set_halp(struct wil6210_priv *wil) in wil6210_set_halp() argument
853 wil_dbg_irq(wil, "set_halp\n"); in wil6210_set_halp()
855 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICS), in wil6210_set_halp()
859 void wil6210_clear_halp(struct wil6210_priv *wil) in wil6210_clear_halp() argument
861 wil_dbg_irq(wil, "clear_halp\n"); in wil6210_clear_halp()
863 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICR), in wil6210_clear_halp()
865 wil6210_unmask_halp(wil); in wil6210_clear_halp()
868 int wil6210_init_irq(struct wil6210_priv *wil, int irq) in wil6210_init_irq() argument
872 wil_dbg_misc(wil, "init_irq: %s, n_msi=%d\n", in wil6210_init_irq()
873 wil->n_msi ? "MSI" : "INTx", wil->n_msi); in wil6210_init_irq()
875 if (wil->use_enhanced_dma_hw) { in wil6210_init_irq()
876 wil->txrx_ops.irq_tx = wil6210_irq_tx_edma; in wil6210_init_irq()
877 wil->txrx_ops.irq_rx = wil6210_irq_rx_edma; in wil6210_init_irq()
879 wil->txrx_ops.irq_tx = wil6210_irq_tx; in wil6210_init_irq()
880 wil->txrx_ops.irq_rx = wil6210_irq_rx; in wil6210_init_irq()
883 if (wil->n_msi == 3) in wil6210_init_irq()
884 rc = wil6210_request_3msi(wil, irq); in wil6210_init_irq()
888 wil->n_msi ? 0 : IRQF_SHARED, in wil6210_init_irq()
889 WIL_NAME, wil); in wil6210_init_irq()
893 void wil6210_fini_irq(struct wil6210_priv *wil, int irq) in wil6210_fini_irq() argument
895 wil_dbg_misc(wil, "fini_irq:\n"); in wil6210_fini_irq()
897 wil_mask_irq(wil); in wil6210_fini_irq()
898 free_irq(irq, wil); in wil6210_fini_irq()
899 if (wil->n_msi == 3) { in wil6210_fini_irq()
900 free_irq(irq + 1, wil); in wil6210_fini_irq()
901 free_irq(irq + 2, wil); in wil6210_fini_irq()