224 	REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);  in ar9003_hw_set_channel()
233 	REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);  in ar9003_hw_set_channel()
239 	REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);  in ar9003_hw_set_channel()
666 	REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);  in ar9003_hw_set_channel_regs()
672 	REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);  in ar9003_hw_set_channel_regs()
674 	REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);  in ar9003_hw_set_channel_regs()
690 	REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);  in ar9003_hw_init_bb()
700 	REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);  in ar9003_hw_set_chain_masks()
701 	REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);  in ar9003_hw_set_chain_masks()
706 	REG_WRITE(ah, AR_SELFGEN_MASK, tx);  in ar9003_hw_set_chain_masks()
734 	REG_WRITE(ah, AR_PCU_MISC_MODE2, val);  in ar9003_hw_override_ini()
737 		REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,  in ar9003_hw_override_ini()
756 			REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);  in ar9003_hw_override_ini()
757 			REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);  in ar9003_hw_override_ini()
758 			REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);  in ar9003_hw_override_ini()
760 			REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);  in ar9003_hw_override_ini()
761 			REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);  in ar9003_hw_override_ini()
762 			REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);  in ar9003_hw_override_ini()
790 		REG_WRITE(ah, reg, val);  in ar9003_hw_prog_ini()
1017 	REG_WRITE(ah, AR_PHY_MODE, rfMode);  in ar9003_hw_set_rfmode()
1022 	REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);  in ar9003_hw_mark_phy_inactive()
1074 	REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);  in ar9003_hw_rfbus_req()
1089 	REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);  in ar9003_hw_rfbus_done()
1498 	REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);  in ar9003_hw_set_radar_params()
1499 	REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);  in ar9003_hw_set_radar_params()
1579 	REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);  in ar9003_hw_antdiv_comb_conf_set()
1613 	REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);  in ar9003_hw_set_bt_ant_diversity()
1625 		REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);  in ar9003_hw_set_bt_ant_diversity()
1636 		REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);  in ar9003_hw_set_bt_ant_diversity()
1652 			REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);  in ar9003_hw_set_bt_ant_diversity()
1687 			REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);  in ar9003_hw_set_bt_ant_diversity()
1827 	REG_WRITE(ah, AR_CR, AR_CR_RXD);  in ar9003_hw_tx99_start()
1828 	REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);  in ar9003_hw_tx99_start()
1829 	REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */  in ar9003_hw_tx99_start()
1830 	REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20);  in ar9003_hw_tx99_start()
1831 	REG_WRITE(ah, AR_TIME_OUT, 0x00000400);  in ar9003_hw_tx99_start()
1832 	REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);  in ar9003_hw_tx99_start()
2037 		REG_WRITE(ah, AR_PHY_RADAR_0, val);  in ar9003_hw_bb_watchdog_check()
2042 		REG_WRITE(ah, AR_PHY_RADAR_0, val);  in ar9003_hw_bb_watchdog_check()
2073 		REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,  in ar9003_hw_bb_watchdog_config()
2079 		REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,  in ar9003_hw_bb_watchdog_config()
2090 	REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,  in ar9003_hw_bb_watchdog_config()
2115 	REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,  in ar9003_hw_bb_watchdog_config()
2136 	REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,  in ar9003_hw_bb_watchdog_read()
2195 		REG_WRITE(ah, AR_PHY_RESTART, val);  in ar9003_hw_disable_phy_restart()