163 			  ar->hw_ce_regs->dst_wr_index_addr, n);  in ath10k_ce_dest_ring_write_index_set()
170 				ar->hw_ce_regs->dst_wr_index_addr);  in ath10k_ce_dest_ring_write_index_get()
178 			  ar->hw_ce_regs->sr_wr_index_addr, n);  in ath10k_ce_src_ring_write_index_set()
185 				ar->hw_ce_regs->sr_wr_index_addr);  in ath10k_ce_src_ring_write_index_get()
209 					 ar->hw_ce_regs->current_srri_addr);  in ath10k_ce_src_ring_read_index_get()
235 			  ar->hw_ce_regs->sr_base_addr, addr);  in ath10k_ce_src_ring_base_addr_set()
243 			  ar->hw_ce_regs->sr_size_addr, n);  in ath10k_ce_src_ring_size_set()
250 	struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs;  in ath10k_ce_src_ring_dmax_set()
264 	struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs;  in ath10k_ce_src_ring_byte_swap_set()
278 	struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs;  in ath10k_ce_dest_ring_byte_swap_set()
310 					 ar->hw_ce_regs->current_drri_addr);  in ath10k_ce_dest_ring_read_index_get()
320 			  ar->hw_ce_regs->dr_base_addr, addr);  in ath10k_ce_dest_ring_base_addr_set()
328 			  ar->hw_ce_regs->dr_size_addr, n);  in ath10k_ce_dest_ring_size_set()
335 	struct ath10k_hw_ce_dst_src_wm_regs *srcr_wm = ar->hw_ce_regs->wm_srcr;  in ath10k_ce_src_ring_highmark_set()
347 	struct ath10k_hw_ce_dst_src_wm_regs *srcr_wm = ar->hw_ce_regs->wm_srcr;  in ath10k_ce_src_ring_lowmark_set()
359 	struct ath10k_hw_ce_dst_src_wm_regs *dstr_wm = ar->hw_ce_regs->wm_dstr;  in ath10k_ce_dest_ring_highmark_set()
371 	struct ath10k_hw_ce_dst_src_wm_regs *dstr_wm = ar->hw_ce_regs->wm_dstr;  in ath10k_ce_dest_ring_lowmark_set()
382 	struct ath10k_hw_ce_host_ie *host_ie = ar->hw_ce_regs->host_ie;  in ath10k_ce_copy_complete_inter_enable()
385 					    ar->hw_ce_regs->host_ie_addr);  in ath10k_ce_copy_complete_inter_enable()
387 	ath10k_ce_write32(ar, ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr,  in ath10k_ce_copy_complete_inter_enable()
394 	struct ath10k_hw_ce_host_ie *host_ie = ar->hw_ce_regs->host_ie;  in ath10k_ce_copy_complete_intr_disable()
397 					    ar->hw_ce_regs->host_ie_addr);  in ath10k_ce_copy_complete_intr_disable()
399 	ath10k_ce_write32(ar, ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr,  in ath10k_ce_copy_complete_intr_disable()
406 	struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs;  in ath10k_ce_watermark_intr_disable()
409 					    ar->hw_ce_regs->host_ie_addr);  in ath10k_ce_watermark_intr_disable()
411 	ath10k_ce_write32(ar, ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr,  in ath10k_ce_watermark_intr_disable()
418 	struct ath10k_hw_ce_misc_regs *misc_regs = ar->hw_ce_regs->misc_regs;  in ath10k_ce_error_intr_enable()
421 					    ar->hw_ce_regs->misc_ie_addr);  in ath10k_ce_error_intr_enable()
424 			  ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr,  in ath10k_ce_error_intr_enable()
431 	struct ath10k_hw_ce_misc_regs *misc_regs = ar->hw_ce_regs->misc_regs;  in ath10k_ce_error_intr_disable()
434 			ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr);  in ath10k_ce_error_intr_disable()
437 			  ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr,  in ath10k_ce_error_intr_disable()
445 	struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs;  in ath10k_ce_engine_int_status_clear()
1205 	struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs;  in ath10k_ce_per_engine_service()
1907 	ath10k_ce_write32(ar, ar->hw_ce_regs->ce_rri_low,  in ath10k_ce_alloc_rri()
1909 	ath10k_ce_write32(ar, ar->hw_ce_regs->ce_rri_high,  in ath10k_ce_alloc_rri()
1914 		ctrl1_regs = ar->hw_ce_regs->ctrl1_regs->addr;  in ath10k_ce_alloc_rri()
1917 		value |= ar->hw_ce_regs->upd->mask;  in ath10k_ce_alloc_rri()