130 		iowrite32be(gumr, &priv->uf_regs->gumr);  in uhdlc_init()
143 	iowrite32be(0, &priv->uf_regs->upsmr);  in uhdlc_init()
157 		iowrite32be(upsmr, &priv->uf_regs->upsmr);  in uhdlc_init()
164 		iowrite32be(gumr, &priv->uf_regs->gumr);  in uhdlc_init()
254 	iowrite32be(priv->dma_rx_bd, &priv->ucc_pram->rbase);  in uhdlc_init()
255 	iowrite32be(priv->dma_tx_bd, &priv->ucc_pram->tbase);  in uhdlc_init()
258 	iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->rstate);  in uhdlc_init()
259 	iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->tstate);  in uhdlc_init()
262 	iowrite32be(CRC_16BIT_MASK, &priv->ucc_pram->c_mask);  in uhdlc_init()
263 	iowrite32be(CRC_16BIT_PRES, &priv->ucc_pram->c_pres);  in uhdlc_init()
299 		iowrite32be(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH,  in uhdlc_init()
310 		iowrite32be(priv->dma_tx_addr + i * MAX_RX_BUF_LENGTH,  in uhdlc_init()
599 	iowrite32be(ucce, uccf->p_ucce);  in ucc_hdlc_irq_handler()
607 			iowrite32be(uccm, uccf->p_uccm);  in ucc_hdlc_irq_handler()
814 	iowrite32be(priv->cmxsi1cr_h, &qe_mux_reg->cmxsi1cr_h);  in resume_clk_config()
815 	iowrite32be(priv->cmxsi1cr_l, &qe_mux_reg->cmxsi1cr_l);  in resume_clk_config()
817 	iowrite32be(priv->cmxsi1syr, &qe_mux_reg->cmxsi1syr);  in resume_clk_config()
886 	iowrite32be(priv->gumr, &uf_regs->gumr);  in uhdlc_resume()
896 	iowrite32be(uccf->ucc_fast_tx_virtual_fifo_base_offset, &uf_regs->utfb);  in uhdlc_resume()
897 	iowrite32be(uccf->ucc_fast_rx_virtual_fifo_base_offset, &uf_regs->urfb);  in uhdlc_resume()
902 	iowrite32be(uf_info->uccm_mask, &uf_regs->uccm);  in uhdlc_resume()
903 	iowrite32be(0xffffffff, &uf_regs->ucce);  in uhdlc_resume()
917 	iowrite32be(0, &uf_regs->upsmr);  in uhdlc_resume()
940 		iowrite32be(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH,  in uhdlc_resume()
951 		iowrite32be(priv->dma_tx_addr + i * MAX_RX_BUF_LENGTH,  in uhdlc_resume()