401 static void scc_writel(u32 bits, struct dscc4_dev_priv *dpriv,  in scc_writel()  function
635 	scc_writel(0x00050000, dpriv, dev, CCR2);
865 	scc_writel(0x00000000, dpriv, dev, CCR0);  in dscc4_init_registers()
867 	scc_writel(LengthCheck | (HDLC_MAX_MRU >> 5), dpriv, dev, RLCR);  in dscc4_init_registers()
875 	scc_writel(0x02408000, dpriv, dev, CCR1);  in dscc4_init_registers()
878 	scc_writel(0x00050008 & ~RxActivate, dpriv, dev, CCR2);  in dscc4_init_registers()
1064 		scc_writel(EventsMask, dpriv, dev, IMR);  in dscc4_open()
1088 	scc_writel(EventsMask, dpriv, dev, IMR);  in dscc4_open()
1091 	scc_writel(TxSccRes | RxSccRes, dpriv, dev, CMDR);  in dscc4_open()
1119 	scc_writel(0xffffffff, dpriv, dev, IMR);  in dscc4_open()
1185 	scc_writel(0xffffffff, dpriv, dev, IMR);  in dscc4_close()
1295 	scc_writel(brr, dpriv, dev, BRR);  in dscc4_set_clock()
1382 	scc_writel(state, dpriv, dev, CCR0);  in dscc4_clock_setting()
1423 	scc_writel(state, dpriv, dev, CCR1);  in dscc4_loopback_setting()
1665 				scc_writel(0x08050008, dpriv, dev, CCR2);  in dscc4_tx_irq()
1809 			scc_writel(RxSccRes, dpriv, dev, CMDR);  in dscc4_rx_irq()