90 		phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1);  in asix_get_phyid()
103 	phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2);  in asix_get_phyid()
116 	return mii_link_ok(&dev->mii);  in asix_get_link()
123 	return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);  in asix_ioctl()
188 	mii_check_media(&dev->mii, 1, 1);  in ax88172_link_reset()
189 	mii_ethtool_gset(&dev->mii, &ecmd);  in ax88172_link_reset()
220 	asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, reset_bits);  in asix_phy_reset()
227 		if (asix_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR)  in asix_phy_reset()
235 		   dev->mii.phy_id);  in asix_phy_reset()
272 	dev->mii.dev = dev->net;  in ax88172_bind()
273 	dev->mii.mdio_read = asix_mdio_read;  in ax88172_bind()
274 	dev->mii.mdio_write = asix_mdio_write;  in ax88172_bind()
275 	dev->mii.phy_id_mask = 0x3f;  in ax88172_bind()
276 	dev->mii.reg_num_mask = 0x1f;  in ax88172_bind()
277 	dev->mii.phy_id = asix_get_phy_addr(dev);  in ax88172_bind()
285 	asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,  in ax88172_bind()
287 	mii_nway_restart(&dev->mii);  in ax88172_bind()
315 	mii_check_media(&dev->mii, 1, 1);  in ax88772_link_reset()
316 	mii_ethtool_gset(&dev->mii, &ecmd);  in ax88772_link_reset()
371 	embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);  in ax88772_hw_reset()
406 	if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,  in ax88772_hw_reset()
466 	embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);  in ax88772a_hw_reset()
498 	if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,  in ax88772a_hw_reset()
519 		phy14h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,  in ax88772a_hw_reset()
521 		phy15h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,  in ax88772a_hw_reset()
523 		phy16h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,  in ax88772a_hw_reset()
532 			asix_mdio_write_nopm(dev->net, dev->mii.phy_id,  in ax88772a_hw_reset()
536 			asix_mdio_write_nopm(dev->net, dev->mii.phy_id,  in ax88772a_hw_reset()
540 			asix_mdio_write_nopm(dev->net, dev->mii.phy_id,  in ax88772a_hw_reset()
617 		asix_mdio_read_nopm(dev->net, dev->mii.phy_id, MII_BMCR);  in ax88772_suspend()
621 		asix_mdio_read_nopm(dev->net, dev->mii.phy_id, MII_ADVERTISE);  in ax88772_suspend()
641 		asix_mdio_write_nopm(dev->net, dev->mii.phy_id, MII_ADVERTISE,  in ax88772_restore_phy()
648 		asix_mdio_write_nopm(dev->net, dev->mii.phy_id, MII_BMCR,  in ax88772_restore_phy()
727 	dev->mii.dev = dev->net;  in ax88772_bind()
728 	dev->mii.mdio_read = asix_mdio_read;  in ax88772_bind()
729 	dev->mii.mdio_write = asix_mdio_write;  in ax88772_bind()
730 	dev->mii.phy_id_mask = 0x1f;  in ax88772_bind()
731 	dev->mii.reg_num_mask = 0x1f;  in ax88772_bind()
732 	dev->mii.phy_id = asix_get_phy_addr(dev);  in ax88772_bind()
803 	reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS);  in marvell_phy_init()
806 	asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL,  in marvell_phy_init()
810 		reg = asix_mdio_read(dev->net, dev->mii.phy_id,  in marvell_phy_init()
816 		asix_mdio_write(dev->net, dev->mii.phy_id,  in marvell_phy_init()
819 		reg = asix_mdio_read(dev->net, dev->mii.phy_id,  in marvell_phy_init()
834 	asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005);  in rtl8211cl_phy_init()
835 	asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0);  in rtl8211cl_phy_init()
836 	asix_mdio_write (dev->net, dev->mii.phy_id, 0x01,  in rtl8211cl_phy_init()
837 		asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080);  in rtl8211cl_phy_init()
838 	asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);  in rtl8211cl_phy_init()
841 		asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002);  in rtl8211cl_phy_init()
842 		asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb);  in rtl8211cl_phy_init()
843 		asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);  in rtl8211cl_phy_init()
851 	u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL);  in marvell_led_status()
870 	asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg);  in marvell_led_status()
939 	asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,  in ax88178_reset()
941 	asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,  in ax88178_reset()
945 	mii_nway_restart(&dev->mii);  in ax88178_reset()
970 	mii_check_media(&dev->mii, 1, 1);  in ax88178_link_reset()
971 	mii_ethtool_gset(&dev->mii, &ecmd);  in ax88178_link_reset()
1085 	dev->mii.dev = dev->net;  in ax88178_bind()
1086 	dev->mii.mdio_read = asix_mdio_read;  in ax88178_bind()
1087 	dev->mii.mdio_write = asix_mdio_write;  in ax88178_bind()
1088 	dev->mii.phy_id_mask = 0x1f;  in ax88178_bind()
1089 	dev->mii.reg_num_mask = 0xff;  in ax88178_bind()
1090 	dev->mii.supports_gmii = 1;  in ax88178_bind()
1091 	dev->mii.phy_id = asix_get_phy_addr(dev);  in ax88178_bind()