Lines Matching refs:phydev

47 static int rockchip_init_tstmode(struct phy_device *phydev)  in rockchip_init_tstmode()  argument
52 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE); in rockchip_init_tstmode()
56 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE); in rockchip_init_tstmode()
60 return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE); in rockchip_init_tstmode()
63 static int rockchip_close_tstmode(struct phy_device *phydev) in rockchip_close_tstmode() argument
66 return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE); in rockchip_close_tstmode()
69 static int rockchip_integrated_phy_analog_init(struct phy_device *phydev) in rockchip_integrated_phy_analog_init() argument
73 ret = rockchip_init_tstmode(phydev); in rockchip_integrated_phy_analog_init()
81 ret = phy_write(phydev, SMI_ADDR_TSTWRITE, 0xB); in rockchip_integrated_phy_analog_init()
84 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTCNTL_WR | WR_ADDR_A7CFG); in rockchip_integrated_phy_analog_init()
88 return rockchip_close_tstmode(phydev); in rockchip_integrated_phy_analog_init()
91 static int rockchip_integrated_phy_config_init(struct phy_device *phydev) in rockchip_integrated_phy_config_init() argument
99 val = phy_read(phydev, MII_INTERNAL_CTRL_STATUS); in rockchip_integrated_phy_config_init()
103 ret = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val); in rockchip_integrated_phy_config_init()
107 return rockchip_integrated_phy_analog_init(phydev); in rockchip_integrated_phy_config_init()
110 static void rockchip_link_change_notify(struct phy_device *phydev) in rockchip_link_change_notify() argument
114 if (phydev->autoneg == AUTONEG_ENABLE) { in rockchip_link_change_notify()
115 int reg = phy_read(phydev, MII_SPECIAL_CONTROL_STATUS); in rockchip_link_change_notify()
118 phydev_err(phydev, "phy_read err: %d.\n", reg); in rockchip_link_change_notify()
127 int bmcr = phy_read(phydev, MII_BMCR); in rockchip_link_change_notify()
130 phydev_err(phydev, "phy_read err: %d.\n", bmcr); in rockchip_link_change_notify()
145 if ((phydev->speed == SPEED_10) && (speed == SPEED_100)) { in rockchip_link_change_notify()
146 int ret = rockchip_integrated_phy_analog_init(phydev); in rockchip_link_change_notify()
148 phydev_err(phydev, "rockchip_integrated_phy_analog_init err: %d.\n", in rockchip_link_change_notify()
153 static int rockchip_set_polarity(struct phy_device *phydev, int polarity) in rockchip_set_polarity() argument
158 reg = phy_read(phydev, MII_INTERNAL_CTRL_STATUS); in rockchip_set_polarity()
179 err = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val); in rockchip_set_polarity()
187 static int rockchip_config_aneg(struct phy_device *phydev) in rockchip_config_aneg() argument
191 err = rockchip_set_polarity(phydev, phydev->mdix); in rockchip_config_aneg()
195 return genphy_config_aneg(phydev); in rockchip_config_aneg()
198 static int rockchip_phy_resume(struct phy_device *phydev) in rockchip_phy_resume() argument
200 genphy_resume(phydev); in rockchip_phy_resume()
202 return rockchip_integrated_phy_config_init(phydev); in rockchip_phy_resume()