Lines Matching refs:phydev
14 int genphy_c45_pma_setup_forced(struct phy_device *phydev) in genphy_c45_pma_setup_forced() argument
19 if (phydev->duplex != DUPLEX_FULL) in genphy_c45_pma_setup_forced()
22 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); in genphy_c45_pma_setup_forced()
26 ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2); in genphy_c45_pma_setup_forced()
37 switch (phydev->speed) { in genphy_c45_pma_setup_forced()
59 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1); in genphy_c45_pma_setup_forced()
63 return phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2); in genphy_c45_pma_setup_forced()
76 int genphy_c45_an_disable_aneg(struct phy_device *phydev) in genphy_c45_an_disable_aneg() argument
80 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); in genphy_c45_an_disable_aneg()
86 return phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, val); in genphy_c45_an_disable_aneg()
98 int genphy_c45_restart_aneg(struct phy_device *phydev) in genphy_c45_restart_aneg() argument
102 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); in genphy_c45_restart_aneg()
108 return phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, val); in genphy_c45_restart_aneg()
123 int genphy_c45_aneg_done(struct phy_device *phydev) in genphy_c45_aneg_done() argument
125 int val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in genphy_c45_aneg_done()
140 int genphy_c45_read_link(struct phy_device *phydev, u32 mmd_mask) in genphy_c45_read_link() argument
153 val = phy_read_mmd(phydev, devad, MDIO_STAT1); in genphy_c45_read_link()
175 int genphy_c45_read_lpa(struct phy_device *phydev) in genphy_c45_read_lpa() argument
180 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA); in genphy_c45_read_lpa()
184 phydev->lp_advertising = mii_lpa_to_ethtool_lpa_t(val); in genphy_c45_read_lpa()
185 phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0; in genphy_c45_read_lpa()
186 phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0; in genphy_c45_read_lpa()
189 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); in genphy_c45_read_lpa()
194 phydev->lp_advertising |= ADVERTISED_10000baseT_Full; in genphy_c45_read_lpa()
204 int genphy_c45_read_pma(struct phy_device *phydev) in genphy_c45_read_pma() argument
208 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); in genphy_c45_read_pma()
214 phydev->speed = SPEED_10; in genphy_c45_read_pma()
217 phydev->speed = SPEED_100; in genphy_c45_read_pma()
220 phydev->speed = SPEED_1000; in genphy_c45_read_pma()
223 phydev->speed = SPEED_10000; in genphy_c45_read_pma()
226 phydev->speed = SPEED_UNKNOWN; in genphy_c45_read_pma()
230 phydev->duplex = DUPLEX_FULL; in genphy_c45_read_pma()
240 int genphy_c45_read_mdix(struct phy_device *phydev) in genphy_c45_read_mdix() argument
244 if (phydev->speed == SPEED_10000) { in genphy_c45_read_mdix()
245 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, in genphy_c45_read_mdix()
252 phydev->mdix = ETH_TP_MDI; in genphy_c45_read_mdix()
256 phydev->mdix = ETH_TP_MDI_X; in genphy_c45_read_mdix()
260 phydev->mdix = ETH_TP_MDI_INVALID; in genphy_c45_read_mdix()
271 int gen10g_config_aneg(struct phy_device *phydev) in gen10g_config_aneg() argument
277 int gen10g_read_status(struct phy_device *phydev) in gen10g_read_status() argument
279 u32 mmd_mask = phydev->c45_ids.devices_in_package; in gen10g_read_status()
283 phydev->speed = SPEED_10000; in gen10g_read_status()
284 phydev->duplex = DUPLEX_FULL; in gen10g_read_status()
289 ret = genphy_c45_read_link(phydev, mmd_mask); in gen10g_read_status()
291 phydev->link = ret > 0 ? 1 : 0; in gen10g_read_status()
297 int gen10g_no_soft_reset(struct phy_device *phydev) in gen10g_no_soft_reset() argument
304 int gen10g_config_init(struct phy_device *phydev) in gen10g_config_init() argument
307 phydev->supported = SUPPORTED_10000baseT_Full; in gen10g_config_init()
308 phydev->advertising = SUPPORTED_10000baseT_Full; in gen10g_config_init()
314 int gen10g_suspend(struct phy_device *phydev) in gen10g_suspend() argument
320 int gen10g_resume(struct phy_device *phydev) in gen10g_resume() argument