139 	u16 reg_val;  in vsc85xx_led_cntl_set()  local
142 	reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL);  in vsc85xx_led_cntl_set()
144 		reg_val &= ~LED_1_MODE_SEL_MASK;  in vsc85xx_led_cntl_set()
145 		reg_val |= (((u16)mode << LED_1_MODE_SEL_POS) &  in vsc85xx_led_cntl_set()
148 		reg_val &= ~LED_0_MODE_SEL_MASK;  in vsc85xx_led_cntl_set()
149 		reg_val |= ((u16)mode & LED_0_MODE_SEL_MASK);  in vsc85xx_led_cntl_set()
151 	rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val);  in vsc85xx_led_cntl_set()
159 	u16 reg_val;  in vsc85xx_mdix_get()  local
161 	reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL);  in vsc85xx_mdix_get()
162 	if (reg_val & HP_AUTO_MDIX_X_OVER_IND_MASK)  in vsc85xx_mdix_get()
173 	u16 reg_val;  in vsc85xx_mdix_set()  local
175 	reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL);  in vsc85xx_mdix_set()
177 		reg_val |= (DISABLE_PAIR_SWAP_CORR_MASK |  in vsc85xx_mdix_set()
181 		reg_val &= ~(DISABLE_PAIR_SWAP_CORR_MASK |  in vsc85xx_mdix_set()
185 	rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val);  in vsc85xx_mdix_set()
193 	reg_val = phy_read(phydev, MSCC_PHY_EXT_MODE_CNTL);  in vsc85xx_mdix_set()
194 	reg_val &= ~(FORCE_MDI_CROSSOVER_MASK);  in vsc85xx_mdix_set()
196 		reg_val |= FORCE_MDI_CROSSOVER_MDI;  in vsc85xx_mdix_set()
198 		reg_val |= FORCE_MDI_CROSSOVER_MDIX;  in vsc85xx_mdix_set()
199 	rc = phy_write(phydev, MSCC_PHY_EXT_MODE_CNTL, reg_val);  in vsc85xx_mdix_set()
213 	u16 reg_val;  in vsc85xx_downshift_get()  local
219 	reg_val = phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL);  in vsc85xx_downshift_get()
220 	reg_val &= DOWNSHIFT_CNTL_MASK;  in vsc85xx_downshift_get()
221 	if (!(reg_val & DOWNSHIFT_EN))  in vsc85xx_downshift_get()
224 		*count = ((reg_val & ~DOWNSHIFT_EN) >> DOWNSHIFT_CNTL_POS) + 2;  in vsc85xx_downshift_get()
234 	u16 reg_val;  in vsc85xx_downshift_set()  local
251 	reg_val = phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL);  in vsc85xx_downshift_set()
252 	reg_val &= ~(DOWNSHIFT_CNTL_MASK);  in vsc85xx_downshift_set()
253 	reg_val |= count;  in vsc85xx_downshift_set()
254 	rc = phy_write(phydev, MSCC_PHY_ACTIPHY_CNTL, reg_val);  in vsc85xx_downshift_set()
268 	u16 reg_val;  in vsc85xx_wol_set()  local
306 	reg_val = phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);  in vsc85xx_wol_set()
308 		reg_val |= SECURE_ON_ENABLE;  in vsc85xx_wol_set()
310 		reg_val &= ~SECURE_ON_ENABLE;  in vsc85xx_wol_set()
311 	phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);  in vsc85xx_wol_set()
319 		reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);  in vsc85xx_wol_set()
320 		reg_val |= MII_VSC85XX_INT_MASK_WOL;  in vsc85xx_wol_set()
321 		rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);  in vsc85xx_wol_set()
326 		reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);  in vsc85xx_wol_set()
327 		reg_val &= (~MII_VSC85XX_INT_MASK_WOL);  in vsc85xx_wol_set()
328 		rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);  in vsc85xx_wol_set()
333 	reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS);  in vsc85xx_wol_set()
345 	u16 reg_val;  in vsc85xx_wol_get()  local
355 	reg_val = phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);  in vsc85xx_wol_get()
356 	if (reg_val & SECURE_ON_ENABLE)  in vsc85xx_wol_get()
444 	u16 reg_val;  in vsc85xx_edge_rate_cntl_set()  local
450 	reg_val = phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);  in vsc85xx_edge_rate_cntl_set()
451 	reg_val &= ~(EDGE_RATE_CNTL_MASK);  in vsc85xx_edge_rate_cntl_set()
452 	reg_val |= (edge_rate << EDGE_RATE_CNTL_POS);  in vsc85xx_edge_rate_cntl_set()
453 	rc = phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);  in vsc85xx_edge_rate_cntl_set()
468 	u16 reg_val;  in vsc85xx_mac_if_set()  local
471 	reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);  in vsc85xx_mac_if_set()
472 	reg_val &= ~(MAC_IF_SELECTION_MASK);  in vsc85xx_mac_if_set()
475 		reg_val |= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS);  in vsc85xx_mac_if_set()
478 		reg_val |= (MAC_IF_SELECTION_RMII << MAC_IF_SELECTION_POS);  in vsc85xx_mac_if_set()
482 		reg_val |= (MAC_IF_SELECTION_GMII << MAC_IF_SELECTION_POS);  in vsc85xx_mac_if_set()
488 	rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val);  in vsc85xx_mac_if_set()
503 	u16 reg_val;  in vsc85xx_default_config()  local
511 	reg_val = phy_read(phydev, MSCC_PHY_RGMII_CNTL);  in vsc85xx_default_config()
512 	reg_val &= ~(RGMII_RX_CLK_DELAY_MASK);  in vsc85xx_default_config()
513 	reg_val |= (RGMII_RX_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS);  in vsc85xx_default_config()
514 	phy_write(phydev, MSCC_PHY_RGMII_CNTL, reg_val);  in vsc85xx_default_config()