Lines Matching refs:DP83867_DEVADDR
26 #define DP83867_DEVADDR 0x1f macro
140 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4); in dp83867_config_port_mirroring()
147 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val); in dp83867_config_port_mirroring()
234 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4); in dp83867_config_init()
236 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val); in dp83867_config_init()
256 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1); in dp83867_config_init()
267 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL); in dp83867_config_init()
278 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val); in dp83867_config_init()
283 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL, in dp83867_config_init()
287 val = phy_read_mmd(phydev, DP83867_DEVADDR, in dp83867_config_init()
294 phy_write_mmd(phydev, DP83867_DEVADDR, in dp83867_config_init()
311 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG); in dp83867_config_init()
314 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, val); in dp83867_config_init()