82 static int dp83822_ack_interrupt(struct phy_device *phydev)  in dp83822_ack_interrupt()  argument
86 	err = phy_read(phydev, MII_DP83822_MISR1);  in dp83822_ack_interrupt()
90 	err = phy_read(phydev, MII_DP83822_MISR2);  in dp83822_ack_interrupt()
97 static int dp83822_set_wol(struct phy_device *phydev,  in dp83822_set_wol()  argument
100 	struct net_device *ndev = phydev->attached_dev;  in dp83822_set_wol()
113 		phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA1,  in dp83822_set_wol()
115 		phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA2,  in dp83822_set_wol()
117 		phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA3,  in dp83822_set_wol()
120 		value = phy_read_mmd(phydev, DP83822_DEVADDR,  in dp83822_set_wol()
128 			phy_write_mmd(phydev, DP83822_DEVADDR,  in dp83822_set_wol()
131 			phy_write_mmd(phydev, DP83822_DEVADDR,  in dp83822_set_wol()
134 			phy_write_mmd(phydev, DP83822_DEVADDR,  in dp83822_set_wol()
144 		phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG,  in dp83822_set_wol()
147 		value = phy_read_mmd(phydev, DP83822_DEVADDR,  in dp83822_set_wol()
150 		phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG,  in dp83822_set_wol()
157 static void dp83822_get_wol(struct phy_device *phydev,  in dp83822_get_wol()  argument
166 	value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);  in dp83822_get_wol()
172 		sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,  in dp83822_get_wol()
177 		sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,  in dp83822_get_wol()
182 		sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,  in dp83822_get_wol()
195 static int dp83822_config_intr(struct phy_device *phydev)  in dp83822_config_intr()  argument
201 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {  in dp83822_config_intr()
202 		misr_status = phy_read(phydev, MII_DP83822_MISR1);  in dp83822_config_intr()
215 		err = phy_write(phydev, MII_DP83822_MISR1, misr_status);  in dp83822_config_intr()
219 		misr_status = phy_read(phydev, MII_DP83822_MISR2);  in dp83822_config_intr()
232 		err = phy_write(phydev, MII_DP83822_MISR2, misr_status);  in dp83822_config_intr()
236 		physcr_status = phy_read(phydev, MII_DP83822_PHYSCR);  in dp83822_config_intr()
243 		err = phy_write(phydev, MII_DP83822_MISR1, 0);  in dp83822_config_intr()
247 		err = phy_write(phydev, MII_DP83822_MISR1, 0);  in dp83822_config_intr()
251 		physcr_status = phy_read(phydev, MII_DP83822_PHYSCR);  in dp83822_config_intr()
258 	return phy_write(phydev, MII_DP83822_PHYSCR, physcr_status);  in dp83822_config_intr()
261 static int dp83822_config_init(struct phy_device *phydev)  in dp83822_config_init()  argument
266 	err = genphy_config_init(phydev);  in dp83822_config_init()
272 	return phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG,  in dp83822_config_init()
276 static int dp83822_phy_reset(struct phy_device *phydev)  in dp83822_phy_reset()  argument
280 	err = phy_write(phydev, MII_DP83822_RESET_CTRL, DP83822_HW_RESET);  in dp83822_phy_reset()
284 	dp83822_config_init(phydev);  in dp83822_phy_reset()
289 static int dp83822_suspend(struct phy_device *phydev)  in dp83822_suspend()  argument
293 	value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);  in dp83822_suspend()
296 		genphy_suspend(phydev);  in dp83822_suspend()
301 static int dp83822_resume(struct phy_device *phydev)  in dp83822_resume()  argument
305 	genphy_resume(phydev);  in dp83822_resume()
307 	value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);  in dp83822_resume()
309 	phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, value |  in dp83822_resume()