79 	bcm_phy_write_misc(phydev, PLL_PLLCTRL_1, 0x0048);  in bcm7xxx_28nm_b0_afe_config_init()
82 	bcm_phy_write_misc(phydev, PLL_PLLCTRL_2, 0x021b);  in bcm7xxx_28nm_b0_afe_config_init()
87 	bcm_phy_write_misc(phydev, PLL_PLLCTRL_4, 0x0e20);  in bcm7xxx_28nm_b0_afe_config_init()
90 	bcm_phy_write_misc(phydev, DSP_TAP10, 0x690b);  in bcm7xxx_28nm_b0_afe_config_init()
98 	bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19);  in bcm7xxx_28nm_b0_afe_config_init()
101 	bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f);  in bcm7xxx_28nm_b0_afe_config_init()
104 	bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);  in bcm7xxx_28nm_b0_afe_config_init()
107 	bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b);  in bcm7xxx_28nm_b0_afe_config_init()
110 	bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800);  in bcm7xxx_28nm_b0_afe_config_init()
118 	bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15);  in bcm7xxx_28nm_d0_afe_config_init()
121 	bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);  in bcm7xxx_28nm_d0_afe_config_init()
124 	bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003);  in bcm7xxx_28nm_d0_afe_config_init()
127 	bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);  in bcm7xxx_28nm_d0_afe_config_init()
130 	bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);  in bcm7xxx_28nm_d0_afe_config_init()
133 	bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);  in bcm7xxx_28nm_d0_afe_config_init()
136 	bcm_phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020);  in bcm7xxx_28nm_d0_afe_config_init()
141 	bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);  in bcm7xxx_28nm_d0_afe_config_init()
147 	bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);  in bcm7xxx_28nm_d0_afe_config_init()
158 	bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);  in bcm7xxx_28nm_e0_plus_afe_config_init()
161 	bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);  in bcm7xxx_28nm_e0_plus_afe_config_init()
164 	bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);  in bcm7xxx_28nm_e0_plus_afe_config_init()
169 	bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);  in bcm7xxx_28nm_e0_plus_afe_config_init()
175 	bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);  in bcm7xxx_28nm_e0_plus_afe_config_init()
186 	bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0xd003);  in bcm7xxx_28nm_a0_patch_afe_config_init()
189 	bcm_phy_write_misc(phydev, DSP_TAP10, 0x791b);  in bcm7xxx_28nm_a0_patch_afe_config_init()
192 	bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x10e3);  in bcm7xxx_28nm_a0_patch_afe_config_init()
195 	bcm_phy_write_misc(phydev, 0x21, 0x2, 0x87f6);  in bcm7xxx_28nm_a0_patch_afe_config_init()
198 	bcm_phy_write_misc(phydev, 0x22, 0x2, 0x017d);  in bcm7xxx_28nm_a0_patch_afe_config_init()
201 	bcm_phy_write_misc(phydev, 0x26, 0x2, 0x0015);  in bcm7xxx_28nm_a0_patch_afe_config_init()