Lines Matching refs:priv
225 struct scc_priv priv[2]; member
234 static void write_scc(struct scc_priv *priv, int reg, int val);
235 static void write_scc_data(struct scc_priv *priv, int val, int fast);
236 static int read_scc(struct scc_priv *priv, int reg);
237 static int read_scc_data(struct scc_priv *priv);
245 static inline void tx_on(struct scc_priv *priv);
246 static inline void rx_on(struct scc_priv *priv);
247 static inline void rx_off(struct scc_priv *priv);
248 static void start_timer(struct scc_priv *priv, int t, int r15);
253 static void rx_isr(struct scc_priv *priv);
254 static void special_condition(struct scc_priv *priv, int rc);
256 static void tx_isr(struct scc_priv *priv);
257 static void es_isr(struct scc_priv *priv);
258 static void tm_isr(struct scc_priv *priv);
293 if (info->priv[0].type == TYPE_TWIN) in dmascc_exit()
295 write_scc(&info->priv[0], R9, FHWRES); in dmascc_exit()
297 hw[info->priv[0].type].io_size); in dmascc_exit()
457 struct scc_priv *priv; in setup_adapter() local
490 priv = &info->priv[0]; in setup_adapter()
491 priv->type = type; in setup_adapter()
492 priv->card_base = card_base; in setup_adapter()
493 priv->scc_cmd = scc_base + SCCA_CMD; in setup_adapter()
494 priv->scc_data = scc_base + SCCA_DATA; in setup_adapter()
495 priv->register_lock = &info->register_lock; in setup_adapter()
498 write_scc(priv, R9, FHWRES | MIE | NV); in setup_adapter()
501 write_scc(priv, R15, SHDLCE); in setup_adapter()
502 if (!read_scc(priv, R15)) { in setup_adapter()
507 write_scc_data(priv, 0, 0); in setup_adapter()
508 if (read_scc(priv, R0) & Tx_BUF_EMP) { in setup_adapter()
516 write_scc(priv, R15, 0); in setup_adapter()
529 write_scc(priv, R15, CTSIE); in setup_adapter()
530 write_scc(priv, R0, RES_EXT_INT); in setup_adapter()
531 write_scc(priv, R1, EXT_INT_ENAB); in setup_adapter()
547 write_scc(priv, R1, 0); in setup_adapter()
548 write_scc(priv, R15, 0); in setup_adapter()
549 write_scc(priv, R0, RES_EXT_INT); in setup_adapter()
563 priv = &info->priv[i]; in setup_adapter()
564 priv->type = type; in setup_adapter()
565 priv->chip = chip; in setup_adapter()
566 priv->dev = dev; in setup_adapter()
567 priv->info = info; in setup_adapter()
568 priv->channel = i; in setup_adapter()
569 spin_lock_init(&priv->ring_lock); in setup_adapter()
570 priv->register_lock = &info->register_lock; in setup_adapter()
571 priv->card_base = card_base; in setup_adapter()
572 priv->scc_cmd = scc_base + (i ? SCCB_CMD : SCCA_CMD); in setup_adapter()
573 priv->scc_data = scc_base + (i ? SCCB_DATA : SCCA_DATA); in setup_adapter()
574 priv->tmr_cnt = tmr_base + (i ? TMR_CNT2 : TMR_CNT1); in setup_adapter()
575 priv->tmr_ctrl = tmr_base + TMR_CTRL; in setup_adapter()
576 priv->tmr_mode = i ? 0xb0 : 0x70; in setup_adapter()
577 priv->param.pclk_hz = hw[type].pclk_hz; in setup_adapter()
578 priv->param.brg_tc = -1; in setup_adapter()
579 priv->param.clocks = TCTRxCP | RCRTxCP; in setup_adapter()
580 priv->param.persist = 256; in setup_adapter()
581 priv->param.dma = -1; in setup_adapter()
582 INIT_WORK(&priv->rx_work, rx_bh); in setup_adapter()
583 dev->ml_priv = priv; in setup_adapter()
613 if (info->priv[0].type == TYPE_TWIN) in setup_adapter()
615 write_scc(&info->priv[0], R9, FHWRES); in setup_adapter()
628 static void write_scc(struct scc_priv *priv, int reg, int val) in write_scc() argument
631 switch (priv->type) { in write_scc()
634 outb(reg, priv->scc_cmd); in write_scc()
635 outb(val, priv->scc_cmd); in write_scc()
639 outb_p(reg, priv->scc_cmd); in write_scc()
640 outb_p(val, priv->scc_cmd); in write_scc()
643 spin_lock_irqsave(priv->register_lock, flags); in write_scc()
644 outb_p(0, priv->card_base + PI_DREQ_MASK); in write_scc()
646 outb_p(reg, priv->scc_cmd); in write_scc()
647 outb_p(val, priv->scc_cmd); in write_scc()
648 outb(1, priv->card_base + PI_DREQ_MASK); in write_scc()
649 spin_unlock_irqrestore(priv->register_lock, flags); in write_scc()
655 static void write_scc_data(struct scc_priv *priv, int val, int fast) in write_scc_data() argument
658 switch (priv->type) { in write_scc_data()
660 outb(val, priv->scc_data); in write_scc_data()
663 outb_p(val, priv->scc_data); in write_scc_data()
667 outb_p(val, priv->scc_data); in write_scc_data()
669 spin_lock_irqsave(priv->register_lock, flags); in write_scc_data()
670 outb_p(0, priv->card_base + PI_DREQ_MASK); in write_scc_data()
671 outb_p(val, priv->scc_data); in write_scc_data()
672 outb(1, priv->card_base + PI_DREQ_MASK); in write_scc_data()
673 spin_unlock_irqrestore(priv->register_lock, flags); in write_scc_data()
680 static int read_scc(struct scc_priv *priv, int reg) in read_scc() argument
684 switch (priv->type) { in read_scc()
687 outb(reg, priv->scc_cmd); in read_scc()
688 return inb(priv->scc_cmd); in read_scc()
691 outb_p(reg, priv->scc_cmd); in read_scc()
692 return inb_p(priv->scc_cmd); in read_scc()
694 spin_lock_irqsave(priv->register_lock, flags); in read_scc()
695 outb_p(0, priv->card_base + PI_DREQ_MASK); in read_scc()
697 outb_p(reg, priv->scc_cmd); in read_scc()
698 rc = inb_p(priv->scc_cmd); in read_scc()
699 outb(1, priv->card_base + PI_DREQ_MASK); in read_scc()
700 spin_unlock_irqrestore(priv->register_lock, flags); in read_scc()
706 static int read_scc_data(struct scc_priv *priv) in read_scc_data() argument
710 switch (priv->type) { in read_scc_data()
712 return inb(priv->scc_data); in read_scc_data()
714 return inb_p(priv->scc_data); in read_scc_data()
716 spin_lock_irqsave(priv->register_lock, flags); in read_scc_data()
717 outb_p(0, priv->card_base + PI_DREQ_MASK); in read_scc_data()
718 rc = inb_p(priv->scc_data); in read_scc_data()
719 outb(1, priv->card_base + PI_DREQ_MASK); in read_scc_data()
720 spin_unlock_irqrestore(priv->register_lock, flags); in read_scc_data()
728 struct scc_priv *priv = dev->ml_priv; in scc_open() local
729 struct scc_info *info = priv->info; in scc_open()
730 int card_base = priv->card_base; in scc_open()
741 if (priv->param.dma >= 0) { in scc_open()
742 if (request_dma(priv->param.dma, "dmascc")) { in scc_open()
748 clear_dma_ff(priv->param.dma); in scc_open()
754 priv->rx_ptr = 0; in scc_open()
755 priv->rx_over = 0; in scc_open()
756 priv->rx_head = priv->rx_tail = priv->rx_count = 0; in scc_open()
757 priv->state = IDLE; in scc_open()
758 priv->tx_head = priv->tx_tail = priv->tx_count = 0; in scc_open()
759 priv->tx_ptr = 0; in scc_open()
762 write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV); in scc_open()
764 write_scc(priv, R4, SDLC | X1CLK); in scc_open()
766 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN); in scc_open()
768 write_scc(priv, R3, Rx8); in scc_open()
770 write_scc(priv, R5, Tx8); in scc_open()
772 write_scc(priv, R6, 0); in scc_open()
774 write_scc(priv, R7, FLAG); in scc_open()
775 switch (priv->chip) { in scc_open()
778 write_scc(priv, R15, SHDLCE); in scc_open()
780 write_scc(priv, R7, AUTOEOM); in scc_open()
781 write_scc(priv, R15, 0); in scc_open()
785 write_scc(priv, R15, SHDLCE); in scc_open()
805 if (priv->param.dma >= 0) { in scc_open()
806 if (priv->type == TYPE_TWIN) in scc_open()
807 write_scc(priv, R7, AUTOEOM | TXFIFOE); in scc_open()
809 write_scc(priv, R7, AUTOEOM); in scc_open()
811 write_scc(priv, R7, AUTOEOM | RXFIFOH); in scc_open()
813 write_scc(priv, R15, 0); in scc_open()
817 write_scc(priv, R10, CRCPS | (priv->param.nrzi ? NRZI : NRZ)); in scc_open()
820 if (priv->param.brg_tc >= 0) { in scc_open()
822 write_scc(priv, R12, priv->param.brg_tc & 0xFF); in scc_open()
823 write_scc(priv, R13, (priv->param.brg_tc >> 8) & 0xFF); in scc_open()
826 write_scc(priv, R14, SSBR | DTRREQ | BRSRC | BRENABL); in scc_open()
828 write_scc(priv, R14, SEARCH | DTRREQ | BRSRC | BRENABL); in scc_open()
831 write_scc(priv, R14, DTRREQ | BRSRC); in scc_open()
835 if (priv->type == TYPE_TWIN) { in scc_open()
838 ~(priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)), in scc_open()
841 write_scc(priv, R11, priv->param.clocks); in scc_open()
842 if ((priv->type == TYPE_TWIN) && !(priv->param.clocks & TRxCOI)) { in scc_open()
845 (priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)), in scc_open()
850 if (priv->type == TYPE_TWIN) { in scc_open()
853 (priv->channel ? TWIN_DTRB_ON : TWIN_DTRA_ON)), in scc_open()
858 priv->rr0 = read_scc(priv, R0); in scc_open()
860 write_scc(priv, R15, DCDIE); in scc_open()
870 struct scc_priv *priv = dev->ml_priv; in scc_close() local
871 struct scc_info *info = priv->info; in scc_close()
872 int card_base = priv->card_base; in scc_close()
876 if (priv->type == TYPE_TWIN) { in scc_close()
879 (priv->channel ? ~TWIN_DTRB_ON : ~TWIN_DTRA_ON)), in scc_close()
884 write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV); in scc_close()
885 if (priv->param.dma >= 0) { in scc_close()
886 if (priv->type == TYPE_TWIN) in scc_close()
888 free_dma(priv->param.dma); in scc_close()
899 struct scc_priv *priv = dev->ml_priv; in scc_ioctl() local
904 (ifr->ifr_data, &priv->param, in scc_ioctl()
914 (&priv->param, ifr->ifr_data, in scc_ioctl()
926 struct scc_priv *priv = dev->ml_priv; in scc_send_packet() local
937 i = priv->tx_head; in scc_send_packet()
938 skb_copy_from_linear_data_offset(skb, 1, priv->tx_buf[i], skb->len - 1); in scc_send_packet()
939 priv->tx_len[i] = skb->len - 1; in scc_send_packet()
943 spin_lock_irqsave(&priv->ring_lock, flags); in scc_send_packet()
945 priv->tx_head = (i + 1) % NUM_TX_BUF; in scc_send_packet()
946 priv->tx_count++; in scc_send_packet()
951 if (priv->tx_count < NUM_TX_BUF) in scc_send_packet()
955 if (priv->state == IDLE) { in scc_send_packet()
957 priv->state = TX_HEAD; in scc_send_packet()
958 priv->tx_start = jiffies; in scc_send_packet()
959 write_scc(priv, R5, TxCRC_ENAB | RTS | TxENAB | Tx8); in scc_send_packet()
960 write_scc(priv, R15, 0); in scc_send_packet()
961 start_timer(priv, priv->param.txdelay, 0); in scc_send_packet()
965 spin_unlock_irqrestore(&priv->ring_lock, flags); in scc_send_packet()
980 static inline void tx_on(struct scc_priv *priv) in tx_on() argument
985 if (priv->param.dma >= 0) { in tx_on()
986 n = (priv->chip == Z85230) ? 3 : 1; in tx_on()
989 set_dma_mode(priv->param.dma, DMA_MODE_WRITE); in tx_on()
990 set_dma_addr(priv->param.dma, in tx_on()
991 (int) priv->tx_buf[priv->tx_tail] + n); in tx_on()
992 set_dma_count(priv->param.dma, in tx_on()
993 priv->tx_len[priv->tx_tail] - n); in tx_on()
996 write_scc(priv, R15, TxUIE); in tx_on()
998 if (priv->type == TYPE_TWIN) in tx_on()
999 outb((priv->param.dma == in tx_on()
1001 priv->card_base + TWIN_DMA_CFG); in tx_on()
1003 write_scc(priv, R1, in tx_on()
1007 spin_lock_irqsave(priv->register_lock, flags); in tx_on()
1009 write_scc_data(priv, in tx_on()
1010 priv->tx_buf[priv->tx_tail][i], 1); in tx_on()
1011 enable_dma(priv->param.dma); in tx_on()
1012 spin_unlock_irqrestore(priv->register_lock, flags); in tx_on()
1014 write_scc(priv, R15, TxUIE); in tx_on()
1015 write_scc(priv, R1, in tx_on()
1017 tx_isr(priv); in tx_on()
1020 if (priv->chip == Z8530) in tx_on()
1021 write_scc(priv, R0, RES_EOM_L); in tx_on()
1025 static inline void rx_on(struct scc_priv *priv) in rx_on() argument
1030 while (read_scc(priv, R0) & Rx_CH_AV) in rx_on()
1031 read_scc_data(priv); in rx_on()
1032 priv->rx_over = 0; in rx_on()
1033 if (priv->param.dma >= 0) { in rx_on()
1036 set_dma_mode(priv->param.dma, DMA_MODE_READ); in rx_on()
1037 set_dma_addr(priv->param.dma, in rx_on()
1038 (int) priv->rx_buf[priv->rx_head]); in rx_on()
1039 set_dma_count(priv->param.dma, BUF_SIZE); in rx_on()
1041 enable_dma(priv->param.dma); in rx_on()
1043 if (priv->type == TYPE_TWIN) { in rx_on()
1044 outb((priv->param.dma == in rx_on()
1046 priv->card_base + TWIN_DMA_CFG); in rx_on()
1049 write_scc(priv, R1, EXT_INT_ENAB | INT_ERR_Rx | in rx_on()
1053 priv->rx_ptr = 0; in rx_on()
1055 write_scc(priv, R1, EXT_INT_ENAB | INT_ALL_Rx | WT_RDY_RT | in rx_on()
1058 write_scc(priv, R0, ERR_RES); in rx_on()
1059 write_scc(priv, R3, RxENABLE | Rx8 | RxCRC_ENAB); in rx_on()
1063 static inline void rx_off(struct scc_priv *priv) in rx_off() argument
1066 write_scc(priv, R3, Rx8); in rx_off()
1068 if (priv->param.dma >= 0 && priv->type == TYPE_TWIN) in rx_off()
1069 outb(0, priv->card_base + TWIN_DMA_CFG); in rx_off()
1071 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN); in rx_off()
1073 if (priv->param.dma >= 0) in rx_off()
1074 disable_dma(priv->param.dma); in rx_off()
1078 static void start_timer(struct scc_priv *priv, int t, int r15) in start_timer() argument
1080 outb(priv->tmr_mode, priv->tmr_ctrl); in start_timer()
1082 tm_isr(priv); in start_timer()
1084 outb(t & 0xFF, priv->tmr_cnt); in start_timer()
1085 outb((t >> 8) & 0xFF, priv->tmr_cnt); in start_timer()
1086 if (priv->type != TYPE_TWIN) { in start_timer()
1087 write_scc(priv, R15, r15 | CTSIE); in start_timer()
1088 priv->rr0 |= CTS; in start_timer()
1105 while ((is = read_scc(&info->priv[0], R3)) && i--) { in z8530_isr()
1107 rx_isr(&info->priv[0]); in z8530_isr()
1109 tx_isr(&info->priv[0]); in z8530_isr()
1111 es_isr(&info->priv[0]); in z8530_isr()
1113 rx_isr(&info->priv[1]); in z8530_isr()
1115 tx_isr(&info->priv[1]); in z8530_isr()
1117 es_isr(&info->priv[1]); in z8530_isr()
1119 write_scc(&info->priv[0], R0, RES_H_IUS); in z8530_isr()
1135 spin_lock(info->priv[0].register_lock); in scc_isr()
1148 if (info->priv[0].type == TYPE_TWIN) { in scc_isr()
1149 int is, card_base = info->priv[0].card_base; in scc_isr()
1156 tm_isr(&info->priv[0]); in scc_isr()
1159 tm_isr(&info->priv[1]); in scc_isr()
1164 spin_unlock(info->priv[0].register_lock); in scc_isr()
1169 static void rx_isr(struct scc_priv *priv) in rx_isr() argument
1171 if (priv->param.dma >= 0) { in rx_isr()
1173 special_condition(priv, read_scc(priv, R1)); in rx_isr()
1174 write_scc(priv, R0, ERR_RES); in rx_isr()
1179 while (read_scc(priv, R0) & Rx_CH_AV) { in rx_isr()
1180 rc = read_scc(priv, R1); in rx_isr()
1181 if (priv->rx_ptr < BUF_SIZE) in rx_isr()
1182 priv->rx_buf[priv->rx_head][priv-> in rx_isr()
1184 read_scc_data(priv); in rx_isr()
1186 priv->rx_over = 2; in rx_isr()
1187 read_scc_data(priv); in rx_isr()
1189 special_condition(priv, rc); in rx_isr()
1195 static void special_condition(struct scc_priv *priv, int rc) in special_condition() argument
1204 priv->rx_over = 1; in special_condition()
1205 if (priv->param.dma < 0) in special_condition()
1206 write_scc(priv, R0, ERR_RES); in special_condition()
1209 if (priv->param.dma >= 0) { in special_condition()
1211 cb = BUF_SIZE - get_dma_residue(priv->param.dma) - in special_condition()
1215 cb = priv->rx_ptr - 2; in special_condition()
1217 if (priv->rx_over) { in special_condition()
1219 priv->dev->stats.rx_errors++; in special_condition()
1220 if (priv->rx_over == 2) in special_condition()
1221 priv->dev->stats.rx_length_errors++; in special_condition()
1223 priv->dev->stats.rx_fifo_errors++; in special_condition()
1224 priv->rx_over = 0; in special_condition()
1228 priv->dev->stats.rx_errors++; in special_condition()
1229 priv->dev->stats.rx_crc_errors++; in special_condition()
1233 if (priv->rx_count < NUM_RX_BUF - 1) { in special_condition()
1235 priv->rx_len[priv->rx_head] = cb; in special_condition()
1236 priv->rx_head = in special_condition()
1237 (priv->rx_head + in special_condition()
1239 priv->rx_count++; in special_condition()
1240 schedule_work(&priv->rx_work); in special_condition()
1242 priv->dev->stats.rx_errors++; in special_condition()
1243 priv->dev->stats.rx_over_errors++; in special_condition()
1248 if (priv->param.dma >= 0) { in special_condition()
1250 set_dma_addr(priv->param.dma, in special_condition()
1251 (int) priv->rx_buf[priv->rx_head]); in special_condition()
1252 set_dma_count(priv->param.dma, BUF_SIZE); in special_condition()
1255 priv->rx_ptr = 0; in special_condition()
1263 struct scc_priv *priv = container_of(ugli_api, struct scc_priv, rx_work); in rx_bh() local
1264 int i = priv->rx_tail; in rx_bh()
1270 spin_lock_irqsave(&priv->ring_lock, flags); in rx_bh()
1271 while (priv->rx_count) { in rx_bh()
1272 spin_unlock_irqrestore(&priv->ring_lock, flags); in rx_bh()
1273 cb = priv->rx_len[i]; in rx_bh()
1278 priv->dev->stats.rx_dropped++; in rx_bh()
1283 memcpy(&data[1], priv->rx_buf[i], cb); in rx_bh()
1284 skb->protocol = ax25_type_trans(skb, priv->dev); in rx_bh()
1286 priv->dev->stats.rx_packets++; in rx_bh()
1287 priv->dev->stats.rx_bytes += cb; in rx_bh()
1289 spin_lock_irqsave(&priv->ring_lock, flags); in rx_bh()
1291 priv->rx_tail = i = (i + 1) % NUM_RX_BUF; in rx_bh()
1292 priv->rx_count--; in rx_bh()
1294 spin_unlock_irqrestore(&priv->ring_lock, flags); in rx_bh()
1298 static void tx_isr(struct scc_priv *priv) in tx_isr() argument
1300 int i = priv->tx_tail, p = priv->tx_ptr; in tx_isr()
1304 if (p == priv->tx_len[i]) { in tx_isr()
1305 write_scc(priv, R0, RES_Tx_P); in tx_isr()
1310 while ((read_scc(priv, R0) & Tx_BUF_EMP) && p < priv->tx_len[i]) { in tx_isr()
1311 write_scc_data(priv, priv->tx_buf[i][p++], 0); in tx_isr()
1315 if (!priv->tx_ptr && p && priv->chip == Z8530) in tx_isr()
1316 write_scc(priv, R0, RES_EOM_L); in tx_isr()
1318 priv->tx_ptr = p; in tx_isr()
1322 static void es_isr(struct scc_priv *priv) in es_isr() argument
1328 rr0 = read_scc(priv, R0); in es_isr()
1329 write_scc(priv, R0, RES_EXT_INT); in es_isr()
1330 drr0 = priv->rr0 ^ rr0; in es_isr()
1331 priv->rr0 = rr0; in es_isr()
1335 if (priv->state == TX_DATA) { in es_isr()
1337 i = priv->tx_tail; in es_isr()
1338 if (priv->param.dma >= 0) { in es_isr()
1339 disable_dma(priv->param.dma); in es_isr()
1341 res = get_dma_residue(priv->param.dma); in es_isr()
1344 res = priv->tx_len[i] - priv->tx_ptr; in es_isr()
1345 priv->tx_ptr = 0; in es_isr()
1348 if (priv->param.dma >= 0 && priv->type == TYPE_TWIN) in es_isr()
1349 outb(0, priv->card_base + TWIN_DMA_CFG); in es_isr()
1351 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN); in es_isr()
1354 priv->dev->stats.tx_errors++; in es_isr()
1355 priv->dev->stats.tx_fifo_errors++; in es_isr()
1357 write_scc(priv, R0, RES_EXT_INT); in es_isr()
1358 write_scc(priv, R0, RES_EXT_INT); in es_isr()
1361 priv->dev->stats.tx_packets++; in es_isr()
1362 priv->dev->stats.tx_bytes += priv->tx_len[i]; in es_isr()
1364 priv->tx_tail = (i + 1) % NUM_TX_BUF; in es_isr()
1365 priv->tx_count--; in es_isr()
1367 netif_wake_queue(priv->dev); in es_isr()
1370 write_scc(priv, R15, 0); in es_isr()
1371 if (priv->tx_count && in es_isr()
1372 (jiffies - priv->tx_start) < priv->param.txtimeout) { in es_isr()
1373 priv->state = TX_PAUSE; in es_isr()
1374 start_timer(priv, priv->param.txpause, 0); in es_isr()
1376 priv->state = TX_TAIL; in es_isr()
1377 start_timer(priv, priv->param.txtail, 0); in es_isr()
1384 switch (priv->state) { in es_isr()
1387 priv->state = DCD_ON; in es_isr()
1388 write_scc(priv, R15, 0); in es_isr()
1389 start_timer(priv, priv->param.dcdon, 0); in es_isr()
1392 switch (priv->state) { in es_isr()
1394 rx_off(priv); in es_isr()
1395 priv->state = DCD_OFF; in es_isr()
1396 write_scc(priv, R15, 0); in es_isr()
1397 start_timer(priv, priv->param.dcdoff, 0); in es_isr()
1403 if ((drr0 & CTS) && (~rr0 & CTS) && priv->type != TYPE_TWIN) in es_isr()
1404 tm_isr(priv); in es_isr()
1409 static void tm_isr(struct scc_priv *priv) in tm_isr() argument
1411 switch (priv->state) { in tm_isr()
1414 tx_on(priv); in tm_isr()
1415 priv->state = TX_DATA; in tm_isr()
1418 write_scc(priv, R5, TxCRC_ENAB | Tx8); in tm_isr()
1419 priv->state = RTS_OFF; in tm_isr()
1420 if (priv->type != TYPE_TWIN) in tm_isr()
1421 write_scc(priv, R15, 0); in tm_isr()
1422 start_timer(priv, priv->param.rtsoff, 0); in tm_isr()
1425 write_scc(priv, R15, DCDIE); in tm_isr()
1426 priv->rr0 = read_scc(priv, R0); in tm_isr()
1427 if (priv->rr0 & DCD) { in tm_isr()
1428 priv->dev->stats.collisions++; in tm_isr()
1429 rx_on(priv); in tm_isr()
1430 priv->state = RX_ON; in tm_isr()
1432 priv->state = WAIT; in tm_isr()
1433 start_timer(priv, priv->param.waittime, DCDIE); in tm_isr()
1437 if (priv->tx_count) { in tm_isr()
1438 priv->state = TX_HEAD; in tm_isr()
1439 priv->tx_start = jiffies; in tm_isr()
1440 write_scc(priv, R5, in tm_isr()
1442 write_scc(priv, R15, 0); in tm_isr()
1443 start_timer(priv, priv->param.txdelay, 0); in tm_isr()
1445 priv->state = IDLE; in tm_isr()
1446 if (priv->type != TYPE_TWIN) in tm_isr()
1447 write_scc(priv, R15, DCDIE); in tm_isr()
1452 write_scc(priv, R15, DCDIE); in tm_isr()
1453 priv->rr0 = read_scc(priv, R0); in tm_isr()
1454 if (priv->rr0 & DCD) { in tm_isr()
1455 rx_on(priv); in tm_isr()
1456 priv->state = RX_ON; in tm_isr()
1458 priv->state = WAIT; in tm_isr()
1459 start_timer(priv, in tm_isr()
1460 random() / priv->param.persist * in tm_isr()
1461 priv->param.slottime, DCDIE); in tm_isr()