Lines Matching refs:gp
117 static u16 __sungem_phy_read(struct gem *gp, int phy_addr, int reg) in __sungem_phy_read() argument
127 writel(cmd, gp->regs + MIF_FRAME); in __sungem_phy_read()
130 cmd = readl(gp->regs + MIF_FRAME); in __sungem_phy_read()
145 struct gem *gp = netdev_priv(dev); in _sungem_phy_read() local
146 return __sungem_phy_read(gp, mii_id, reg); in _sungem_phy_read()
149 static inline u16 sungem_phy_read(struct gem *gp, int reg) in sungem_phy_read() argument
151 return __sungem_phy_read(gp, gp->mii_phy_addr, reg); in sungem_phy_read()
154 static void __sungem_phy_write(struct gem *gp, int phy_addr, int reg, u16 val) in __sungem_phy_write() argument
165 writel(cmd, gp->regs + MIF_FRAME); in __sungem_phy_write()
168 cmd = readl(gp->regs + MIF_FRAME); in __sungem_phy_write()
178 struct gem *gp = netdev_priv(dev); in _sungem_phy_write() local
179 __sungem_phy_write(gp, mii_id, reg, val & 0xffff); in _sungem_phy_write()
182 static inline void sungem_phy_write(struct gem *gp, int reg, u16 val) in sungem_phy_write() argument
184 __sungem_phy_write(gp, gp->mii_phy_addr, reg, val); in sungem_phy_write()
187 static inline void gem_enable_ints(struct gem *gp) in gem_enable_ints() argument
190 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK); in gem_enable_ints()
193 static inline void gem_disable_ints(struct gem *gp) in gem_disable_ints() argument
196 writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK); in gem_disable_ints()
197 (void)readl(gp->regs + GREG_IMASK); /* write posting */ in gem_disable_ints()
200 static void gem_get_cell(struct gem *gp) in gem_get_cell() argument
202 BUG_ON(gp->cell_enabled < 0); in gem_get_cell()
203 gp->cell_enabled++; in gem_get_cell()
205 if (gp->cell_enabled == 1) { in gem_get_cell()
207 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1); in gem_get_cell()
214 static void gem_put_cell(struct gem *gp) in gem_put_cell() argument
216 BUG_ON(gp->cell_enabled <= 0); in gem_put_cell()
217 gp->cell_enabled--; in gem_put_cell()
219 if (gp->cell_enabled == 0) { in gem_put_cell()
221 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0); in gem_put_cell()
227 static inline void gem_netif_stop(struct gem *gp) in gem_netif_stop() argument
229 netif_trans_update(gp->dev); /* prevent tx timeout */ in gem_netif_stop()
230 napi_disable(&gp->napi); in gem_netif_stop()
231 netif_tx_disable(gp->dev); in gem_netif_stop()
234 static inline void gem_netif_start(struct gem *gp) in gem_netif_start() argument
240 netif_wake_queue(gp->dev); in gem_netif_start()
241 napi_enable(&gp->napi); in gem_netif_start()
244 static void gem_schedule_reset(struct gem *gp) in gem_schedule_reset() argument
246 gp->reset_task_pending = 1; in gem_schedule_reset()
247 schedule_work(&gp->reset_task); in gem_schedule_reset()
250 static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits) in gem_handle_mif_event() argument
252 if (netif_msg_intr(gp)) in gem_handle_mif_event()
253 printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name); in gem_handle_mif_event()
256 static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) in gem_pcs_interrupt() argument
258 u32 pcs_istat = readl(gp->regs + PCS_ISTAT); in gem_pcs_interrupt()
261 if (netif_msg_intr(gp)) in gem_pcs_interrupt()
263 gp->dev->name, pcs_istat); in gem_pcs_interrupt()
274 pcs_miistat = readl(gp->regs + PCS_MIISTAT); in gem_pcs_interrupt()
277 (readl(gp->regs + PCS_MIISTAT) & in gem_pcs_interrupt()
292 netif_carrier_on(gp->dev); in gem_pcs_interrupt()
295 netif_carrier_off(gp->dev); in gem_pcs_interrupt()
299 if (!timer_pending(&gp->link_timer)) in gem_pcs_interrupt()
306 static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) in gem_txmac_interrupt() argument
308 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT); in gem_txmac_interrupt()
310 if (netif_msg_intr(gp)) in gem_txmac_interrupt()
312 gp->dev->name, txmac_stat); in gem_txmac_interrupt()
359 static int gem_rxmac_reset(struct gem *gp) in gem_rxmac_reset() argument
361 struct net_device *dev = gp->dev; in gem_rxmac_reset()
367 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST); in gem_rxmac_reset()
369 if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD)) in gem_rxmac_reset()
378 writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB, in gem_rxmac_reset()
379 gp->regs + MAC_RXCFG); in gem_rxmac_reset()
381 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB)) in gem_rxmac_reset()
391 writel(0, gp->regs + RXDMA_CFG); in gem_rxmac_reset()
393 if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE)) in gem_rxmac_reset()
405 writel(gp->swrst_base | GREG_SWRST_RXRST, in gem_rxmac_reset()
406 gp->regs + GREG_SWRST); in gem_rxmac_reset()
408 if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST)) in gem_rxmac_reset()
419 struct gem_rxd *rxd = &gp->init_block->rxd[i]; in gem_rxmac_reset()
421 if (gp->rx_skbs[i] == NULL) { in gem_rxmac_reset()
426 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp)); in gem_rxmac_reset()
428 gp->rx_new = gp->rx_old = 0; in gem_rxmac_reset()
431 desc_dma = (u64) gp->gblock_dvma; in gem_rxmac_reset()
433 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI); in gem_rxmac_reset()
434 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW); in gem_rxmac_reset()
435 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK); in gem_rxmac_reset()
438 writel(val, gp->regs + RXDMA_CFG); in gem_rxmac_reset()
439 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN) in gem_rxmac_reset()
442 gp->regs + RXDMA_BLANK); in gem_rxmac_reset()
446 gp->regs + RXDMA_BLANK); in gem_rxmac_reset()
447 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF); in gem_rxmac_reset()
448 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON); in gem_rxmac_reset()
449 writel(val, gp->regs + RXDMA_PTHRESH); in gem_rxmac_reset()
450 val = readl(gp->regs + RXDMA_CFG); in gem_rxmac_reset()
451 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG); in gem_rxmac_reset()
452 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK); in gem_rxmac_reset()
453 val = readl(gp->regs + MAC_RXCFG); in gem_rxmac_reset()
454 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); in gem_rxmac_reset()
459 static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) in gem_rxmac_interrupt() argument
461 u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT); in gem_rxmac_interrupt()
464 if (netif_msg_intr(gp)) in gem_rxmac_interrupt()
466 gp->dev->name, rxmac_stat); in gem_rxmac_interrupt()
469 u32 smac = readl(gp->regs + MAC_SMACHINE); in gem_rxmac_interrupt()
475 ret = gem_rxmac_reset(gp); in gem_rxmac_interrupt()
493 static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) in gem_mac_interrupt() argument
495 u32 mac_cstat = readl(gp->regs + MAC_CSTAT); in gem_mac_interrupt()
497 if (netif_msg_intr(gp)) in gem_mac_interrupt()
499 gp->dev->name, mac_cstat); in gem_mac_interrupt()
506 gp->pause_entered++; in gem_mac_interrupt()
509 gp->pause_last_time_recvd = (mac_cstat >> 16); in gem_mac_interrupt()
514 static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) in gem_mif_interrupt() argument
516 u32 mif_status = readl(gp->regs + MIF_STATUS); in gem_mif_interrupt()
522 gem_handle_mif_event(gp, reg_val, changed_bits); in gem_mif_interrupt()
527 static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) in gem_pci_interrupt() argument
529 u32 pci_estat = readl(gp->regs + GREG_PCIESTAT); in gem_pci_interrupt()
531 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN && in gem_pci_interrupt()
532 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) { in gem_pci_interrupt()
553 pci_read_config_word(gp->pdev, PCI_STATUS, in gem_pci_interrupt()
577 pci_write_config_word(gp->pdev, in gem_pci_interrupt()
590 static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status) in gem_abnormal_irq() argument
594 if (netif_msg_rx_err(gp)) in gem_abnormal_irq()
596 gp->dev->name); in gem_abnormal_irq()
602 if (netif_msg_rx_err(gp)) in gem_abnormal_irq()
604 gp->dev->name); in gem_abnormal_irq()
611 if (gem_pcs_interrupt(dev, gp, gem_status)) in gem_abnormal_irq()
616 if (gem_txmac_interrupt(dev, gp, gem_status)) in gem_abnormal_irq()
621 if (gem_rxmac_interrupt(dev, gp, gem_status)) in gem_abnormal_irq()
626 if (gem_mac_interrupt(dev, gp, gem_status)) in gem_abnormal_irq()
631 if (gem_mif_interrupt(dev, gp, gem_status)) in gem_abnormal_irq()
636 if (gem_pci_interrupt(dev, gp, gem_status)) in gem_abnormal_irq()
643 static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status) in gem_tx() argument
647 entry = gp->tx_old; in gem_tx()
656 if (netif_msg_tx_done(gp)) in gem_tx()
658 gp->dev->name, entry); in gem_tx()
659 skb = gp->tx_skbs[entry]; in gem_tx()
676 gp->tx_skbs[entry] = NULL; in gem_tx()
680 txd = &gp->init_block->txd[entry]; in gem_tx()
685 pci_unmap_page(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE); in gem_tx()
692 gp->tx_old = entry; in gem_tx()
702 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))) { in gem_tx()
707 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1)) in gem_tx()
713 static __inline__ void gem_post_rxds(struct gem *gp, int limit) in gem_post_rxds() argument
717 cluster_start = curr = (gp->rx_new & ~(4 - 1)); in gem_post_rxds()
725 &gp->init_block->rxd[cluster_start]; in gem_post_rxds()
727 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp)); in gem_post_rxds()
739 writel(kick, gp->regs + RXDMA_KICK); in gem_post_rxds()
757 static int gem_rx(struct gem *gp, int work_to_do) in gem_rx() argument
759 struct net_device *dev = gp->dev; in gem_rx()
763 if (netif_msg_rx_status(gp)) in gem_rx()
765 gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new); in gem_rx()
767 entry = gp->rx_new; in gem_rx()
769 done = readl(gp->regs + RXDMA_DONE); in gem_rx()
771 struct gem_rxd *rxd = &gp->init_block->rxd[entry]; in gem_rx()
791 done = readl(gp->regs + RXDMA_DONE); in gem_rx()
799 skb = gp->rx_skbs[entry]; in gem_rx()
819 new_skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC); in gem_rx()
824 pci_unmap_page(gp->pdev, dma_addr, in gem_rx()
825 RX_BUF_ALLOC_SIZE(gp), in gem_rx()
827 gp->rx_skbs[entry] = new_skb; in gem_rx()
828 skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET)); in gem_rx()
829 rxd->buffer = cpu_to_le64(pci_map_page(gp->pdev, in gem_rx()
832 RX_BUF_ALLOC_SIZE(gp), in gem_rx()
848 pci_dma_sync_single_for_cpu(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); in gem_rx()
850 pci_dma_sync_single_for_device(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); in gem_rx()
863 skb->protocol = eth_type_trans(skb, gp->dev); in gem_rx()
865 napi_gro_receive(&gp->napi, skb); in gem_rx()
874 gem_post_rxds(gp, entry); in gem_rx()
876 gp->rx_new = entry; in gem_rx()
879 netdev_info(gp->dev, "Memory squeeze, deferring packet\n"); in gem_rx()
886 struct gem *gp = container_of(napi, struct gem, napi); in gem_poll() local
887 struct net_device *dev = gp->dev; in gem_poll()
893 if (unlikely(gp->status & GREG_STAT_ABNORMAL)) { in gem_poll()
903 reset = gem_abnormal_irq(dev, gp, gp->status); in gem_poll()
906 gem_schedule_reset(gp); in gem_poll()
913 gem_tx(dev, gp, gp->status); in gem_poll()
920 work_done += gem_rx(gp, budget - work_done); in gem_poll()
925 gp->status = readl(gp->regs + GREG_STAT); in gem_poll()
926 } while (gp->status & GREG_STAT_NAPI); in gem_poll()
929 gem_enable_ints(gp); in gem_poll()
937 struct gem *gp = netdev_priv(dev); in gem_interrupt() local
939 if (napi_schedule_prep(&gp->napi)) { in gem_interrupt()
940 u32 gem_status = readl(gp->regs + GREG_STAT); in gem_interrupt()
943 napi_enable(&gp->napi); in gem_interrupt()
946 if (netif_msg_intr(gp)) in gem_interrupt()
948 gp->dev->name, gem_status); in gem_interrupt()
950 gp->status = gem_status; in gem_interrupt()
951 gem_disable_ints(gp); in gem_interrupt()
952 __napi_schedule(&gp->napi); in gem_interrupt()
965 struct gem *gp = netdev_priv(dev); in gem_poll_controller() local
967 disable_irq(gp->pdev->irq); in gem_poll_controller()
968 gem_interrupt(gp->pdev->irq, dev); in gem_poll_controller()
969 enable_irq(gp->pdev->irq); in gem_poll_controller()
975 struct gem *gp = netdev_priv(dev); in gem_tx_timeout() local
980 readl(gp->regs + TXDMA_CFG), in gem_tx_timeout()
981 readl(gp->regs + MAC_TXSTAT), in gem_tx_timeout()
982 readl(gp->regs + MAC_TXCFG)); in gem_tx_timeout()
984 readl(gp->regs + RXDMA_CFG), in gem_tx_timeout()
985 readl(gp->regs + MAC_RXSTAT), in gem_tx_timeout()
986 readl(gp->regs + MAC_RXCFG)); in gem_tx_timeout()
988 gem_schedule_reset(gp); in gem_tx_timeout()
1003 struct gem *gp = netdev_priv(dev); in gem_start_xmit() local
1017 if (unlikely(TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1))) { in gem_start_xmit()
1026 entry = gp->tx_new; in gem_start_xmit()
1027 gp->tx_skbs[entry] = skb; in gem_start_xmit()
1030 struct gem_txd *txd = &gp->init_block->txd[entry]; in gem_start_xmit()
1035 mapping = pci_map_page(gp->pdev, in gem_start_xmit()
1061 first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data), in gem_start_xmit()
1073 mapping = skb_frag_dma_map(&gp->pdev->dev, this_frag, in gem_start_xmit()
1079 txd = &gp->init_block->txd[entry]; in gem_start_xmit()
1089 txd = &gp->init_block->txd[first_entry]; in gem_start_xmit()
1096 gp->tx_new = entry; in gem_start_xmit()
1097 if (unlikely(TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))) { in gem_start_xmit()
1106 if (TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1)) in gem_start_xmit()
1109 if (netif_msg_tx_queued(gp)) in gem_start_xmit()
1113 writel(gp->tx_new, gp->regs + TXDMA_KICK); in gem_start_xmit()
1118 static void gem_pcs_reset(struct gem *gp) in gem_pcs_reset() argument
1124 val = readl(gp->regs + PCS_MIICTRL); in gem_pcs_reset()
1126 writel(val, gp->regs + PCS_MIICTRL); in gem_pcs_reset()
1129 while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) { in gem_pcs_reset()
1135 netdev_warn(gp->dev, "PCS reset bit would not clear\n"); in gem_pcs_reset()
1138 static void gem_pcs_reinit_adv(struct gem *gp) in gem_pcs_reinit_adv() argument
1145 val = readl(gp->regs + PCS_CFG); in gem_pcs_reinit_adv()
1147 writel(val, gp->regs + PCS_CFG); in gem_pcs_reinit_adv()
1152 val = readl(gp->regs + PCS_MIIADV); in gem_pcs_reinit_adv()
1155 writel(val, gp->regs + PCS_MIIADV); in gem_pcs_reinit_adv()
1160 val = readl(gp->regs + PCS_MIICTRL); in gem_pcs_reinit_adv()
1163 writel(val, gp->regs + PCS_MIICTRL); in gem_pcs_reinit_adv()
1165 val = readl(gp->regs + PCS_CFG); in gem_pcs_reinit_adv()
1167 writel(val, gp->regs + PCS_CFG); in gem_pcs_reinit_adv()
1173 val = readl(gp->regs + PCS_SCTRL); in gem_pcs_reinit_adv()
1174 if (gp->phy_type == phy_serialink) in gem_pcs_reinit_adv()
1178 writel(val, gp->regs + PCS_SCTRL); in gem_pcs_reinit_adv()
1183 static void gem_reset(struct gem *gp) in gem_reset() argument
1189 writel(0xffffffff, gp->regs + GREG_IMASK); in gem_reset()
1192 writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST, in gem_reset()
1193 gp->regs + GREG_SWRST); in gem_reset()
1199 val = readl(gp->regs + GREG_SWRST); in gem_reset()
1205 netdev_err(gp->dev, "SW reset is ghetto\n"); in gem_reset()
1207 if (gp->phy_type == phy_serialink || gp->phy_type == phy_serdes) in gem_reset()
1208 gem_pcs_reinit_adv(gp); in gem_reset()
1211 static void gem_start_dma(struct gem *gp) in gem_start_dma() argument
1216 val = readl(gp->regs + TXDMA_CFG); in gem_start_dma()
1217 writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG); in gem_start_dma()
1218 val = readl(gp->regs + RXDMA_CFG); in gem_start_dma()
1219 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG); in gem_start_dma()
1220 val = readl(gp->regs + MAC_TXCFG); in gem_start_dma()
1221 writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG); in gem_start_dma()
1222 val = readl(gp->regs + MAC_RXCFG); in gem_start_dma()
1223 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); in gem_start_dma()
1225 (void) readl(gp->regs + MAC_RXCFG); in gem_start_dma()
1228 gem_enable_ints(gp); in gem_start_dma()
1230 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK); in gem_start_dma()
1235 static void gem_stop_dma(struct gem *gp) in gem_stop_dma() argument
1240 val = readl(gp->regs + TXDMA_CFG); in gem_stop_dma()
1241 writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG); in gem_stop_dma()
1242 val = readl(gp->regs + RXDMA_CFG); in gem_stop_dma()
1243 writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG); in gem_stop_dma()
1244 val = readl(gp->regs + MAC_TXCFG); in gem_stop_dma()
1245 writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG); in gem_stop_dma()
1246 val = readl(gp->regs + MAC_RXCFG); in gem_stop_dma()
1247 writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); in gem_stop_dma()
1249 (void) readl(gp->regs + MAC_RXCFG); in gem_stop_dma()
1256 static void gem_begin_auto_negotiation(struct gem *gp, in gem_begin_auto_negotiation() argument
1269 if (gp->phy_type != phy_mii_mdio0 && in gem_begin_auto_negotiation()
1270 gp->phy_type != phy_mii_mdio1) in gem_begin_auto_negotiation()
1274 if (found_mii_phy(gp)) in gem_begin_auto_negotiation()
1275 features = gp->phy_mii.def->features; in gem_begin_auto_negotiation()
1280 if (gp->phy_mii.advertising != 0) in gem_begin_auto_negotiation()
1281 advertise &= gp->phy_mii.advertising; in gem_begin_auto_negotiation()
1283 autoneg = gp->want_autoneg; in gem_begin_auto_negotiation()
1284 speed = gp->phy_mii.speed; in gem_begin_auto_negotiation()
1285 duplex = gp->phy_mii.duplex; in gem_begin_auto_negotiation()
1320 if (!netif_device_present(gp->dev)) { in gem_begin_auto_negotiation()
1321 gp->phy_mii.autoneg = gp->want_autoneg = autoneg; in gem_begin_auto_negotiation()
1322 gp->phy_mii.speed = speed; in gem_begin_auto_negotiation()
1323 gp->phy_mii.duplex = duplex; in gem_begin_auto_negotiation()
1328 gp->want_autoneg = autoneg; in gem_begin_auto_negotiation()
1330 if (found_mii_phy(gp)) in gem_begin_auto_negotiation()
1331 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise); in gem_begin_auto_negotiation()
1332 gp->lstate = link_aneg; in gem_begin_auto_negotiation()
1334 if (found_mii_phy(gp)) in gem_begin_auto_negotiation()
1335 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex); in gem_begin_auto_negotiation()
1336 gp->lstate = link_force_ok; in gem_begin_auto_negotiation()
1340 gp->timer_ticks = 0; in gem_begin_auto_negotiation()
1341 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10)); in gem_begin_auto_negotiation()
1347 static int gem_set_link_modes(struct gem *gp) in gem_set_link_modes() argument
1349 struct netdev_queue *txq = netdev_get_tx_queue(gp->dev, 0); in gem_set_link_modes()
1357 if (found_mii_phy(gp)) { in gem_set_link_modes()
1358 if (gp->phy_mii.def->ops->read_link(&gp->phy_mii)) in gem_set_link_modes()
1360 full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL); in gem_set_link_modes()
1361 speed = gp->phy_mii.speed; in gem_set_link_modes()
1362 pause = gp->phy_mii.pause; in gem_set_link_modes()
1363 } else if (gp->phy_type == phy_serialink || in gem_set_link_modes()
1364 gp->phy_type == phy_serdes) { in gem_set_link_modes()
1365 u32 pcs_lpa = readl(gp->regs + PCS_MIILP); in gem_set_link_modes()
1367 if ((pcs_lpa & PCS_MIIADV_FD) || gp->phy_type == phy_serdes) in gem_set_link_modes()
1372 netif_info(gp, link, gp->dev, "Link is up at %d Mbps, %s-duplex\n", in gem_set_link_modes()
1387 writel(val, gp->regs + MAC_TXCFG); in gem_set_link_modes()
1391 (gp->phy_type == phy_mii_mdio0 || in gem_set_link_modes()
1392 gp->phy_type == phy_mii_mdio1)) { in gem_set_link_modes()
1401 writel(val, gp->regs + MAC_XIFCFG); in gem_set_link_modes()
1407 val = readl(gp->regs + MAC_TXCFG); in gem_set_link_modes()
1408 writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG); in gem_set_link_modes()
1410 val = readl(gp->regs + MAC_RXCFG); in gem_set_link_modes()
1411 writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG); in gem_set_link_modes()
1413 val = readl(gp->regs + MAC_TXCFG); in gem_set_link_modes()
1414 writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG); in gem_set_link_modes()
1416 val = readl(gp->regs + MAC_RXCFG); in gem_set_link_modes()
1417 writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG); in gem_set_link_modes()
1420 if (gp->phy_type == phy_serialink || in gem_set_link_modes()
1421 gp->phy_type == phy_serdes) { in gem_set_link_modes()
1422 u32 pcs_lpa = readl(gp->regs + PCS_MIILP); in gem_set_link_modes()
1429 writel(512, gp->regs + MAC_STIME); in gem_set_link_modes()
1431 writel(64, gp->regs + MAC_STIME); in gem_set_link_modes()
1432 val = readl(gp->regs + MAC_MCCFG); in gem_set_link_modes()
1437 writel(val, gp->regs + MAC_MCCFG); in gem_set_link_modes()
1439 gem_start_dma(gp); in gem_set_link_modes()
1443 if (netif_msg_link(gp)) { in gem_set_link_modes()
1445 netdev_info(gp->dev, in gem_set_link_modes()
1447 gp->rx_fifo_sz, in gem_set_link_modes()
1448 gp->rx_pause_off, in gem_set_link_modes()
1449 gp->rx_pause_on); in gem_set_link_modes()
1451 netdev_info(gp->dev, "Pause is disabled\n"); in gem_set_link_modes()
1458 static int gem_mdio_link_not_up(struct gem *gp) in gem_mdio_link_not_up() argument
1460 switch (gp->lstate) { in gem_mdio_link_not_up()
1462 netif_info(gp, link, gp->dev, in gem_mdio_link_not_up()
1464 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, in gem_mdio_link_not_up()
1465 gp->last_forced_speed, DUPLEX_HALF); in gem_mdio_link_not_up()
1466 gp->timer_ticks = 5; in gem_mdio_link_not_up()
1467 gp->lstate = link_force_ok; in gem_mdio_link_not_up()
1474 if (gp->phy_mii.def->magic_aneg) in gem_mdio_link_not_up()
1476 netif_info(gp, link, gp->dev, "switching to forced 100bt\n"); in gem_mdio_link_not_up()
1478 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100, in gem_mdio_link_not_up()
1480 gp->timer_ticks = 5; in gem_mdio_link_not_up()
1481 gp->lstate = link_force_try; in gem_mdio_link_not_up()
1488 if (gp->phy_mii.speed == SPEED_100) { in gem_mdio_link_not_up()
1489 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10, in gem_mdio_link_not_up()
1491 gp->timer_ticks = 5; in gem_mdio_link_not_up()
1492 netif_info(gp, link, gp->dev, in gem_mdio_link_not_up()
1504 struct gem *gp = from_timer(gp, t, link_timer); in gem_link_timer() local
1505 struct net_device *dev = gp->dev; in gem_link_timer()
1509 if (gp->reset_task_pending) in gem_link_timer()
1512 if (gp->phy_type == phy_serialink || in gem_link_timer()
1513 gp->phy_type == phy_serdes) { in gem_link_timer()
1514 u32 val = readl(gp->regs + PCS_MIISTAT); in gem_link_timer()
1517 val = readl(gp->regs + PCS_MIISTAT); in gem_link_timer()
1520 if (gp->lstate == link_up) in gem_link_timer()
1523 gp->lstate = link_up; in gem_link_timer()
1525 (void)gem_set_link_modes(gp); in gem_link_timer()
1529 if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) { in gem_link_timer()
1535 if (gp->lstate == link_force_try && gp->want_autoneg) { in gem_link_timer()
1536 gp->lstate = link_force_ret; in gem_link_timer()
1537 gp->last_forced_speed = gp->phy_mii.speed; in gem_link_timer()
1538 gp->timer_ticks = 5; in gem_link_timer()
1539 if (netif_msg_link(gp)) in gem_link_timer()
1542 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising); in gem_link_timer()
1543 } else if (gp->lstate != link_up) { in gem_link_timer()
1544 gp->lstate = link_up; in gem_link_timer()
1546 if (gem_set_link_modes(gp)) in gem_link_timer()
1553 if (gp->lstate == link_up) { in gem_link_timer()
1554 gp->lstate = link_down; in gem_link_timer()
1555 netif_info(gp, link, dev, "Link down\n"); in gem_link_timer()
1557 gem_schedule_reset(gp); in gem_link_timer()
1560 } else if (++gp->timer_ticks > 10) { in gem_link_timer()
1561 if (found_mii_phy(gp)) in gem_link_timer()
1562 restart_aneg = gem_mdio_link_not_up(gp); in gem_link_timer()
1568 gem_begin_auto_negotiation(gp, NULL); in gem_link_timer()
1572 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10)); in gem_link_timer()
1575 static void gem_clean_rings(struct gem *gp) in gem_clean_rings() argument
1577 struct gem_init_block *gb = gp->init_block; in gem_clean_rings()
1586 if (gp->rx_skbs[i] != NULL) { in gem_clean_rings()
1587 skb = gp->rx_skbs[i]; in gem_clean_rings()
1589 pci_unmap_page(gp->pdev, dma_addr, in gem_clean_rings()
1590 RX_BUF_ALLOC_SIZE(gp), in gem_clean_rings()
1593 gp->rx_skbs[i] = NULL; in gem_clean_rings()
1601 if (gp->tx_skbs[i] != NULL) { in gem_clean_rings()
1605 skb = gp->tx_skbs[i]; in gem_clean_rings()
1606 gp->tx_skbs[i] = NULL; in gem_clean_rings()
1613 pci_unmap_page(gp->pdev, dma_addr, in gem_clean_rings()
1625 static void gem_init_rings(struct gem *gp) in gem_init_rings() argument
1627 struct gem_init_block *gb = gp->init_block; in gem_init_rings()
1628 struct net_device *dev = gp->dev; in gem_init_rings()
1632 gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0; in gem_init_rings()
1634 gem_clean_rings(gp); in gem_init_rings()
1636 gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN, in gem_init_rings()
1643 skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_KERNEL); in gem_init_rings()
1650 gp->rx_skbs[i] = skb; in gem_init_rings()
1651 skb_put(skb, (gp->rx_buf_sz + RX_OFFSET)); in gem_init_rings()
1652 dma_addr = pci_map_page(gp->pdev, in gem_init_rings()
1655 RX_BUF_ALLOC_SIZE(gp), in gem_init_rings()
1659 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp)); in gem_init_rings()
1674 static void gem_init_phy(struct gem *gp) in gem_init_phy() argument
1679 mifcfg = readl(gp->regs + MIF_CFG); in gem_init_phy()
1681 writel(mifcfg, gp->regs + MIF_CFG); in gem_init_phy()
1683 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) { in gem_init_phy()
1692 pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0); in gem_init_phy()
1698 sungem_phy_write(gp, MII_BMCR, BMCR_RESET); in gem_init_phy()
1700 if (sungem_phy_read(gp, MII_BMCR) != 0xffff) in gem_init_phy()
1703 netdev_warn(gp->dev, "GMAC PHY not responding !\n"); in gem_init_phy()
1707 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN && in gem_init_phy()
1708 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) { in gem_init_phy()
1712 if (gp->phy_type == phy_mii_mdio0 || in gem_init_phy()
1713 gp->phy_type == phy_mii_mdio1) { in gem_init_phy()
1715 } else if (gp->phy_type == phy_serialink) { in gem_init_phy()
1721 writel(val, gp->regs + PCS_DMODE); in gem_init_phy()
1724 if (gp->phy_type == phy_mii_mdio0 || in gem_init_phy()
1725 gp->phy_type == phy_mii_mdio1) { in gem_init_phy()
1727 sungem_phy_probe(&gp->phy_mii, gp->mii_phy_addr); in gem_init_phy()
1730 if (gp->phy_mii.def && gp->phy_mii.def->ops->init) in gem_init_phy()
1731 gp->phy_mii.def->ops->init(&gp->phy_mii); in gem_init_phy()
1733 gem_pcs_reset(gp); in gem_init_phy()
1734 gem_pcs_reinit_adv(gp); in gem_init_phy()
1738 gp->timer_ticks = 0; in gem_init_phy()
1739 gp->lstate = link_down; in gem_init_phy()
1740 netif_carrier_off(gp->dev); in gem_init_phy()
1743 if (gp->phy_type == phy_mii_mdio0 || in gem_init_phy()
1744 gp->phy_type == phy_mii_mdio1) in gem_init_phy()
1745 netdev_info(gp->dev, "Found %s PHY\n", in gem_init_phy()
1746 gp->phy_mii.def ? gp->phy_mii.def->name : "no"); in gem_init_phy()
1748 gem_begin_auto_negotiation(gp, NULL); in gem_init_phy()
1751 static void gem_init_dma(struct gem *gp) in gem_init_dma() argument
1753 u64 desc_dma = (u64) gp->gblock_dvma; in gem_init_dma()
1757 writel(val, gp->regs + TXDMA_CFG); in gem_init_dma()
1759 writel(desc_dma >> 32, gp->regs + TXDMA_DBHI); in gem_init_dma()
1760 writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW); in gem_init_dma()
1763 writel(0, gp->regs + TXDMA_KICK); in gem_init_dma()
1767 writel(val, gp->regs + RXDMA_CFG); in gem_init_dma()
1769 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI); in gem_init_dma()
1770 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW); in gem_init_dma()
1772 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK); in gem_init_dma()
1774 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF); in gem_init_dma()
1775 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON); in gem_init_dma()
1776 writel(val, gp->regs + RXDMA_PTHRESH); in gem_init_dma()
1778 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN) in gem_init_dma()
1781 gp->regs + RXDMA_BLANK); in gem_init_dma()
1785 gp->regs + RXDMA_BLANK); in gem_init_dma()
1788 static u32 gem_setup_multicast(struct gem *gp) in gem_setup_multicast() argument
1793 if ((gp->dev->flags & IFF_ALLMULTI) || in gem_setup_multicast()
1794 (netdev_mc_count(gp->dev) > 256)) { in gem_setup_multicast()
1796 writel(0xffff, gp->regs + MAC_HASH0 + (i << 2)); in gem_setup_multicast()
1798 } else if (gp->dev->flags & IFF_PROMISC) { in gem_setup_multicast()
1807 netdev_for_each_mc_addr(ha, gp->dev) { in gem_setup_multicast()
1813 writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2)); in gem_setup_multicast()
1820 static void gem_init_mac(struct gem *gp) in gem_init_mac() argument
1822 unsigned char *e = &gp->dev->dev_addr[0]; in gem_init_mac()
1824 writel(0x1bf0, gp->regs + MAC_SNDPAUSE); in gem_init_mac()
1826 writel(0x00, gp->regs + MAC_IPG0); in gem_init_mac()
1827 writel(0x08, gp->regs + MAC_IPG1); in gem_init_mac()
1828 writel(0x04, gp->regs + MAC_IPG2); in gem_init_mac()
1829 writel(0x40, gp->regs + MAC_STIME); in gem_init_mac()
1830 writel(0x40, gp->regs + MAC_MINFSZ); in gem_init_mac()
1833 writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ); in gem_init_mac()
1835 writel(0x07, gp->regs + MAC_PASIZE); in gem_init_mac()
1836 writel(0x04, gp->regs + MAC_JAMSIZE); in gem_init_mac()
1837 writel(0x10, gp->regs + MAC_ATTLIM); in gem_init_mac()
1838 writel(0x8808, gp->regs + MAC_MCTYPE); in gem_init_mac()
1840 writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED); in gem_init_mac()
1842 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0); in gem_init_mac()
1843 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1); in gem_init_mac()
1844 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2); in gem_init_mac()
1846 writel(0, gp->regs + MAC_ADDR3); in gem_init_mac()
1847 writel(0, gp->regs + MAC_ADDR4); in gem_init_mac()
1848 writel(0, gp->regs + MAC_ADDR5); in gem_init_mac()
1850 writel(0x0001, gp->regs + MAC_ADDR6); in gem_init_mac()
1851 writel(0xc200, gp->regs + MAC_ADDR7); in gem_init_mac()
1852 writel(0x0180, gp->regs + MAC_ADDR8); in gem_init_mac()
1854 writel(0, gp->regs + MAC_AFILT0); in gem_init_mac()
1855 writel(0, gp->regs + MAC_AFILT1); in gem_init_mac()
1856 writel(0, gp->regs + MAC_AFILT2); in gem_init_mac()
1857 writel(0, gp->regs + MAC_AF21MSK); in gem_init_mac()
1858 writel(0, gp->regs + MAC_AF0MSK); in gem_init_mac()
1860 gp->mac_rx_cfg = gem_setup_multicast(gp); in gem_init_mac()
1862 gp->mac_rx_cfg |= MAC_RXCFG_SFCS; in gem_init_mac()
1864 writel(0, gp->regs + MAC_NCOLL); in gem_init_mac()
1865 writel(0, gp->regs + MAC_FASUCC); in gem_init_mac()
1866 writel(0, gp->regs + MAC_ECOLL); in gem_init_mac()
1867 writel(0, gp->regs + MAC_LCOLL); in gem_init_mac()
1868 writel(0, gp->regs + MAC_DTIMER); in gem_init_mac()
1869 writel(0, gp->regs + MAC_PATMPS); in gem_init_mac()
1870 writel(0, gp->regs + MAC_RFCTR); in gem_init_mac()
1871 writel(0, gp->regs + MAC_LERR); in gem_init_mac()
1872 writel(0, gp->regs + MAC_AERR); in gem_init_mac()
1873 writel(0, gp->regs + MAC_FCSERR); in gem_init_mac()
1874 writel(0, gp->regs + MAC_RXCVERR); in gem_init_mac()
1879 writel(0, gp->regs + MAC_TXCFG); in gem_init_mac()
1880 writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG); in gem_init_mac()
1881 writel(0, gp->regs + MAC_MCCFG); in gem_init_mac()
1882 writel(0, gp->regs + MAC_XIFCFG); in gem_init_mac()
1888 writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK); in gem_init_mac()
1889 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK); in gem_init_mac()
1894 writel(0xffffffff, gp->regs + MAC_MCMASK); in gem_init_mac()
1898 if (gp->has_wol) in gem_init_mac()
1899 writel(0, gp->regs + WOL_WAKECSR); in gem_init_mac()
1902 static void gem_init_pause_thresholds(struct gem *gp) in gem_init_pause_thresholds() argument
1911 if (gp->rx_fifo_sz <= (2 * 1024)) { in gem_init_pause_thresholds()
1912 gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz; in gem_init_pause_thresholds()
1914 int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63; in gem_init_pause_thresholds()
1915 int off = (gp->rx_fifo_sz - (max_frame * 2)); in gem_init_pause_thresholds()
1918 gp->rx_pause_off = off; in gem_init_pause_thresholds()
1919 gp->rx_pause_on = on; in gem_init_pause_thresholds()
1927 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) in gem_init_pause_thresholds()
1934 writel(cfg, gp->regs + GREG_CFG); in gem_init_pause_thresholds()
1939 if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) { in gem_init_pause_thresholds()
1942 writel(cfg, gp->regs + GREG_CFG); in gem_init_pause_thresholds()
1946 static int gem_check_invariants(struct gem *gp) in gem_check_invariants() argument
1948 struct pci_dev *pdev = gp->pdev; in gem_check_invariants()
1956 gp->phy_type = phy_mii_mdio0; in gem_check_invariants()
1957 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64; in gem_check_invariants()
1958 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64; in gem_check_invariants()
1959 gp->swrst_base = 0; in gem_check_invariants()
1961 mif_cfg = readl(gp->regs + MIF_CFG); in gem_check_invariants()
1964 writel(mif_cfg, gp->regs + MIF_CFG); in gem_check_invariants()
1965 writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE); in gem_check_invariants()
1966 writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG); in gem_check_invariants()
1972 if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC) in gem_check_invariants()
1973 gp->mii_phy_addr = 1; in gem_check_invariants()
1975 gp->mii_phy_addr = 0; in gem_check_invariants()
1980 mif_cfg = readl(gp->regs + MIF_CFG); in gem_check_invariants()
1999 gp->phy_type = phy_mii_mdio1; in gem_check_invariants()
2001 writel(mif_cfg, gp->regs + MIF_CFG); in gem_check_invariants()
2003 gp->phy_type = phy_mii_mdio0; in gem_check_invariants()
2005 writel(mif_cfg, gp->regs + MIF_CFG); in gem_check_invariants()
2010 p = of_get_property(gp->of_node, "shared-pins", NULL); in gem_check_invariants()
2012 gp->phy_type = phy_serdes; in gem_check_invariants()
2015 gp->phy_type = phy_serialink; in gem_check_invariants()
2017 if (gp->phy_type == phy_mii_mdio1 || in gem_check_invariants()
2018 gp->phy_type == phy_mii_mdio0) { in gem_check_invariants()
2022 gp->mii_phy_addr = i; in gem_check_invariants()
2023 if (sungem_phy_read(gp, MII_BMCR) != 0xffff) in gem_check_invariants()
2031 gp->phy_type = phy_serdes; in gem_check_invariants()
2036 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64; in gem_check_invariants()
2037 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64; in gem_check_invariants()
2041 if (gp->tx_fifo_sz != (9 * 1024) || in gem_check_invariants()
2042 gp->rx_fifo_sz != (20 * 1024)) { in gem_check_invariants()
2044 gp->tx_fifo_sz, gp->rx_fifo_sz); in gem_check_invariants()
2047 gp->swrst_base = 0; in gem_check_invariants()
2049 if (gp->tx_fifo_sz != (2 * 1024) || in gem_check_invariants()
2050 gp->rx_fifo_sz != (2 * 1024)) { in gem_check_invariants()
2052 gp->tx_fifo_sz, gp->rx_fifo_sz); in gem_check_invariants()
2055 gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT; in gem_check_invariants()
2062 static void gem_reinit_chip(struct gem *gp) in gem_reinit_chip() argument
2065 gem_reset(gp); in gem_reinit_chip()
2068 gem_disable_ints(gp); in gem_reinit_chip()
2071 gem_init_rings(gp); in gem_reinit_chip()
2074 gem_init_pause_thresholds(gp); in gem_reinit_chip()
2077 gem_init_dma(gp); in gem_reinit_chip()
2078 gem_init_mac(gp); in gem_reinit_chip()
2082 static void gem_stop_phy(struct gem *gp, int wol) in gem_stop_phy() argument
2094 mifcfg = readl(gp->regs + MIF_CFG); in gem_stop_phy()
2096 writel(mifcfg, gp->regs + MIF_CFG); in gem_stop_phy()
2098 if (wol && gp->has_wol) { in gem_stop_phy()
2099 unsigned char *e = &gp->dev->dev_addr[0]; in gem_stop_phy()
2104 gp->regs + MAC_RXCFG); in gem_stop_phy()
2105 writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0); in gem_stop_phy()
2106 writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1); in gem_stop_phy()
2107 writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2); in gem_stop_phy()
2109 writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT); in gem_stop_phy()
2111 if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0) in gem_stop_phy()
2113 writel(csr, gp->regs + WOL_WAKECSR); in gem_stop_phy()
2115 writel(0, gp->regs + MAC_RXCFG); in gem_stop_phy()
2116 (void)readl(gp->regs + MAC_RXCFG); in gem_stop_phy()
2124 writel(0, gp->regs + MAC_TXCFG); in gem_stop_phy()
2125 writel(0, gp->regs + MAC_XIFCFG); in gem_stop_phy()
2126 writel(0, gp->regs + TXDMA_CFG); in gem_stop_phy()
2127 writel(0, gp->regs + RXDMA_CFG); in gem_stop_phy()
2130 gem_reset(gp); in gem_stop_phy()
2131 writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST); in gem_stop_phy()
2132 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST); in gem_stop_phy()
2134 if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend) in gem_stop_phy()
2135 gp->phy_mii.def->ops->suspend(&gp->phy_mii); in gem_stop_phy()
2140 writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG); in gem_stop_phy()
2141 writel(0, gp->regs + MIF_BBCLK); in gem_stop_phy()
2142 writel(0, gp->regs + MIF_BBDATA); in gem_stop_phy()
2143 writel(0, gp->regs + MIF_BBOENAB); in gem_stop_phy()
2144 writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG); in gem_stop_phy()
2145 (void) readl(gp->regs + MAC_XIFCFG); in gem_stop_phy()
2151 struct gem *gp = netdev_priv(dev); in gem_do_start() local
2155 gem_get_cell(gp); in gem_do_start()
2158 rc = pci_enable_device(gp->pdev); in gem_do_start()
2165 gem_put_cell(gp); in gem_do_start()
2168 pci_set_master(gp->pdev); in gem_do_start()
2171 gem_reinit_chip(gp); in gem_do_start()
2174 rc = request_irq(gp->pdev->irq, gem_interrupt, in gem_do_start()
2179 gem_reset(gp); in gem_do_start()
2180 gem_clean_rings(gp); in gem_do_start()
2181 gem_put_cell(gp); in gem_do_start()
2191 gem_netif_start(gp); in gem_do_start()
2197 gem_init_phy(gp); in gem_do_start()
2204 struct gem *gp = netdev_priv(dev); in gem_do_stop() local
2207 gem_netif_stop(gp); in gem_do_stop()
2214 gem_disable_ints(gp); in gem_do_stop()
2217 del_timer_sync(&gp->link_timer); in gem_do_stop()
2228 gp->reset_task_pending = 0; in gem_do_stop()
2231 gem_stop_dma(gp); in gem_do_stop()
2234 gem_reset(gp); in gem_do_stop()
2238 gem_clean_rings(gp); in gem_do_stop()
2241 free_irq(gp->pdev->irq, (void *) dev); in gem_do_stop()
2244 gem_stop_phy(gp, wol); in gem_do_stop()
2247 pci_disable_device(gp->pdev); in gem_do_stop()
2251 gem_put_cell(gp); in gem_do_stop()
2256 struct gem *gp = container_of(work, struct gem, reset_task); in gem_reset_task() local
2266 if (!netif_device_present(gp->dev) || in gem_reset_task()
2267 !netif_running(gp->dev) || in gem_reset_task()
2268 !gp->reset_task_pending) { in gem_reset_task()
2274 del_timer_sync(&gp->link_timer); in gem_reset_task()
2277 gem_netif_stop(gp); in gem_reset_task()
2280 gem_reinit_chip(gp); in gem_reset_task()
2281 if (gp->lstate == link_up) in gem_reset_task()
2282 gem_set_link_modes(gp); in gem_reset_task()
2285 gem_netif_start(gp); in gem_reset_task()
2288 gp->reset_task_pending = 0; in gem_reset_task()
2293 if (gp->lstate != link_up) in gem_reset_task()
2294 gem_begin_auto_negotiation(gp, NULL); in gem_reset_task()
2296 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10)); in gem_reset_task()
2323 struct gem *gp = netdev_priv(dev); in gem_suspend() local
2339 (gp->wake_on_lan && netif_running(dev)) ? in gem_suspend()
2348 gp->asleep_wol = !!gp->wake_on_lan; in gem_suspend()
2349 gem_do_stop(dev, gp->asleep_wol); in gem_suspend()
2360 struct gem *gp = netdev_priv(dev); in gem_resume() local
2382 if (gp->asleep_wol) in gem_resume()
2383 gem_put_cell(gp); in gem_resume()
2394 struct gem *gp = netdev_priv(dev); in gem_get_stats() local
2407 if (WARN_ON(!gp->cell_enabled)) in gem_get_stats()
2410 dev->stats.rx_crc_errors += readl(gp->regs + MAC_FCSERR); in gem_get_stats()
2411 writel(0, gp->regs + MAC_FCSERR); in gem_get_stats()
2413 dev->stats.rx_frame_errors += readl(gp->regs + MAC_AERR); in gem_get_stats()
2414 writel(0, gp->regs + MAC_AERR); in gem_get_stats()
2416 dev->stats.rx_length_errors += readl(gp->regs + MAC_LERR); in gem_get_stats()
2417 writel(0, gp->regs + MAC_LERR); in gem_get_stats()
2419 dev->stats.tx_aborted_errors += readl(gp->regs + MAC_ECOLL); in gem_get_stats()
2421 (readl(gp->regs + MAC_ECOLL) + readl(gp->regs + MAC_LCOLL)); in gem_get_stats()
2422 writel(0, gp->regs + MAC_ECOLL); in gem_get_stats()
2423 writel(0, gp->regs + MAC_LCOLL); in gem_get_stats()
2431 struct gem *gp = netdev_priv(dev); in gem_set_mac_address() local
2444 if (WARN_ON(!gp->cell_enabled)) in gem_set_mac_address()
2447 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0); in gem_set_mac_address()
2448 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1); in gem_set_mac_address()
2449 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2); in gem_set_mac_address()
2456 struct gem *gp = netdev_priv(dev); in gem_set_multicast() local
2464 if (gp->reset_task_pending || WARN_ON(!gp->cell_enabled)) in gem_set_multicast()
2467 rxcfg = readl(gp->regs + MAC_RXCFG); in gem_set_multicast()
2468 rxcfg_new = gem_setup_multicast(gp); in gem_set_multicast()
2472 gp->mac_rx_cfg = rxcfg_new; in gem_set_multicast()
2474 writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); in gem_set_multicast()
2475 while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) { in gem_set_multicast()
2484 writel(rxcfg, gp->regs + MAC_RXCFG); in gem_set_multicast()
2497 struct gem *gp = netdev_priv(dev); in gem_change_mtu() local
2506 if (WARN_ON(!gp->cell_enabled)) in gem_change_mtu()
2509 gem_netif_stop(gp); in gem_change_mtu()
2510 gem_reinit_chip(gp); in gem_change_mtu()
2511 if (gp->lstate == link_up) in gem_change_mtu()
2512 gem_set_link_modes(gp); in gem_change_mtu()
2513 gem_netif_start(gp); in gem_change_mtu()
2520 struct gem *gp = netdev_priv(dev); in gem_get_drvinfo() local
2524 strlcpy(info->bus_info, pci_name(gp->pdev), sizeof(info->bus_info)); in gem_get_drvinfo()
2530 struct gem *gp = netdev_priv(dev); in gem_get_link_ksettings() local
2533 if (gp->phy_type == phy_mii_mdio0 || in gem_get_link_ksettings()
2534 gp->phy_type == phy_mii_mdio1) { in gem_get_link_ksettings()
2535 if (gp->phy_mii.def) in gem_get_link_ksettings()
2536 supported = gp->phy_mii.def->features; in gem_get_link_ksettings()
2546 cmd->base.autoneg = gp->want_autoneg; in gem_get_link_ksettings()
2547 cmd->base.speed = gp->phy_mii.speed; in gem_get_link_ksettings()
2548 cmd->base.duplex = gp->phy_mii.duplex; in gem_get_link_ksettings()
2549 advertising = gp->phy_mii.advertising; in gem_get_link_ksettings()
2570 if (gp->phy_type == phy_serdes) { in gem_get_link_ksettings()
2577 if (gp->lstate == link_up) in gem_get_link_ksettings()
2595 struct gem *gp = netdev_priv(dev); in gem_set_link_ksettings() local
2620 if (netif_device_present(gp->dev)) { in gem_set_link_ksettings()
2621 del_timer_sync(&gp->link_timer); in gem_set_link_ksettings()
2622 gem_begin_auto_negotiation(gp, cmd); in gem_set_link_ksettings()
2630 struct gem *gp = netdev_priv(dev); in gem_nway_reset() local
2632 if (!gp->want_autoneg) in gem_nway_reset()
2636 if (netif_device_present(gp->dev)) { in gem_nway_reset()
2637 del_timer_sync(&gp->link_timer); in gem_nway_reset()
2638 gem_begin_auto_negotiation(gp, NULL); in gem_nway_reset()
2646 struct gem *gp = netdev_priv(dev); in gem_get_msglevel() local
2647 return gp->msg_enable; in gem_get_msglevel()
2652 struct gem *gp = netdev_priv(dev); in gem_set_msglevel() local
2653 gp->msg_enable = value; in gem_set_msglevel()
2664 struct gem *gp = netdev_priv(dev); in gem_get_wol() local
2667 if (gp->has_wol) { in gem_get_wol()
2669 wol->wolopts = gp->wake_on_lan; in gem_get_wol()
2678 struct gem *gp = netdev_priv(dev); in gem_set_wol() local
2680 if (!gp->has_wol) in gem_set_wol()
2682 gp->wake_on_lan = wol->wolopts & WOL_SUPPORTED_MASK; in gem_set_wol()
2700 struct gem *gp = netdev_priv(dev); in gem_ioctl() local
2711 data->phy_id = gp->mii_phy_addr; in gem_ioctl()
2715 data->val_out = __sungem_phy_read(gp, data->phy_id & 0x1f, in gem_ioctl()
2721 __sungem_phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f, in gem_ioctl()
2781 static int gem_get_device_address(struct gem *gp) in gem_get_device_address() argument
2784 struct net_device *dev = gp->dev; in gem_get_device_address()
2787 addr = of_get_property(gp->of_node, "local-mac-address", NULL); in gem_get_device_address()
2799 get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr); in gem_get_device_address()
2809 struct gem *gp = netdev_priv(dev); in gem_remove_one() local
2814 cancel_work_sync(&gp->reset_task); in gem_remove_one()
2819 gp->init_block, in gem_remove_one()
2820 gp->gblock_dvma); in gem_remove_one()
2821 iounmap(gp->regs); in gem_remove_one()
2847 struct gem *gp; in gem_init_one() local
2896 dev = alloc_etherdev(sizeof(*gp)); in gem_init_one()
2903 gp = netdev_priv(dev); in gem_init_one()
2911 gp->pdev = pdev; in gem_init_one()
2912 gp->dev = dev; in gem_init_one()
2914 gp->msg_enable = DEFAULT_MSG; in gem_init_one()
2916 timer_setup(&gp->link_timer, gem_link_timer, 0); in gem_init_one()
2918 INIT_WORK(&gp->reset_task, gem_reset_task); in gem_init_one()
2920 gp->lstate = link_down; in gem_init_one()
2921 gp->timer_ticks = 0; in gem_init_one()
2924 gp->regs = ioremap(gemreg_base, gemreg_len); in gem_init_one()
2925 if (!gp->regs) { in gem_init_one()
2935 gp->of_node = pci_device_to_OF_node(pdev); in gem_init_one()
2940 gp->has_wol = 1; in gem_init_one()
2943 gem_get_cell(gp); in gem_init_one()
2946 gem_reset(gp); in gem_init_one()
2949 gp->phy_mii.dev = dev; in gem_init_one()
2950 gp->phy_mii.mdio_read = _sungem_phy_read; in gem_init_one()
2951 gp->phy_mii.mdio_write = _sungem_phy_write; in gem_init_one()
2953 gp->phy_mii.platform_data = gp->of_node; in gem_init_one()
2956 gp->want_autoneg = 1; in gem_init_one()
2959 if (gem_check_invariants(gp)) { in gem_init_one()
2967 gp->init_block = (struct gem_init_block *) in gem_init_one()
2969 &gp->gblock_dvma); in gem_init_one()
2970 if (!gp->init_block) { in gem_init_one()
2976 err = gem_get_device_address(gp); in gem_init_one()
2981 netif_napi_add(dev, &gp->napi, gem_poll, 64); in gem_init_one()
3010 gem_put_cell(gp); in gem_init_one()
3020 gem_put_cell(gp); in gem_init_one()
3021 iounmap(gp->regs); in gem_init_one()