13 	u32 value = readl(ioaddr + XGMAC_DMA_MODE);  in dwxgmac2_dma_reset()
25 	u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);  in dwxgmac2_dma_init()
36 	u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan));  in dwxgmac2_dma_init_chan()
52 	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));  in dwxgmac2_dma_init_rx_chan()
67 	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));  in dwxgmac2_dma_init_tx_chan()
78 	u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);  in dwxgmac2_dma_axi()
130 	u32 value = readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));  in dwxgmac2_dma_rx_mode()
153 	value = readl(ioaddr + XGMAC_MTL_QINTEN(channel));  in dwxgmac2_dma_rx_mode()
160 	u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));  in dwxgmac2_dma_tx_mode()
211 	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));  in dwxgmac2_dma_start_tx()
215 	value = readl(ioaddr + XGMAC_TX_CONFIG);  in dwxgmac2_dma_start_tx()
224 	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));  in dwxgmac2_dma_stop_tx()
228 	value = readl(ioaddr + XGMAC_TX_CONFIG);  in dwxgmac2_dma_stop_tx()
237 	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));  in dwxgmac2_dma_start_rx()
241 	value = readl(ioaddr + XGMAC_RX_CONFIG);  in dwxgmac2_dma_start_rx()
250 	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));  in dwxgmac2_dma_stop_rx()
254 	value = readl(ioaddr + XGMAC_RX_CONFIG);  in dwxgmac2_dma_stop_rx()
262 	u32 intr_status = readl(ioaddr + XGMAC_DMA_CH_STATUS(chan));  in dwxgmac2_dma_interrupt()
282 			u32 value = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan));  in dwxgmac2_dma_interrupt()
306 	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE0);  in dwxgmac2_get_hw_feature()
317 	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE1);  in dwxgmac2_get_hw_feature()
325 	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE2);  in dwxgmac2_get_hw_feature()
367 	u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));  in dwxgmac2_enable_tso()
381 	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));  in dwxgmac2_set_bfsize()