Lines Matching refs:DMA_CONTROL
62 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_start_tx()
64 writel(value, ioaddr + DMA_CONTROL); in dwmac_dma_start_tx()
69 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_stop_tx()
71 writel(value, ioaddr + DMA_CONTROL); in dwmac_dma_stop_tx()
76 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_start_rx()
78 writel(value, ioaddr + DMA_CONTROL); in dwmac_dma_start_rx()
83 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_stop_rx()
85 writel(value, ioaddr + DMA_CONTROL); in dwmac_dma_stop_rx()
231 u32 csr6 = readl(ioaddr + DMA_CONTROL); in dwmac_dma_flush_tx_fifo()
232 writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL); in dwmac_dma_flush_tx_fifo()
234 do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF)); in dwmac_dma_flush_tx_fifo()