19 	u32 value = readl(ioaddr + DMA_BUS_MODE);  in dwmac4_dma_reset()
27 		if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET))  in dwmac4_dma_reset()
50 	u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));  in dwmac4_dma_start_tx()
55 	value = readl(ioaddr + GMAC_CONFIG);  in dwmac4_dma_start_tx()
62 	u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));  in dwmac4_dma_stop_tx()
67 	value = readl(ioaddr + GMAC_CONFIG);  in dwmac4_dma_stop_tx()
74 	u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan));  in dwmac4_dma_start_rx()
80 	value = readl(ioaddr + GMAC_CONFIG);  in dwmac4_dma_start_rx()
87 	u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan));  in dwmac4_dma_stop_rx()
92 	value = readl(ioaddr + GMAC_CONFIG);  in dwmac4_dma_stop_rx()
129 	u32 intr_status = readl(ioaddr + DMA_CHAN_STATUS(chan));  in dwmac4_dma_interrupt()
156 			value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan));  in dwmac4_dma_interrupt()
199 	u32 value = readl(ioaddr + GMAC_CONFIG);  in stmmac_dwmac4_set_mac()
215 	hi_addr = readl(ioaddr + high);  in stmmac_dwmac4_get_mac_addr()
216 	lo_addr = readl(ioaddr + low);  in stmmac_dwmac4_get_mac_addr()