299 static void netsec_write(struct netsec_priv *priv, u32 reg_addr, u32 val)  in netsec_write()  function
353 	netsec_write(priv, MAC_REG_DATA, value);  in netsec_mac_write()
354 	netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_WRITE);  in netsec_mac_write()
363 	netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_READ);  in netsec_mac_read()
510 	netsec_write(priv, NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT,  in netsec_et_set_coalesce()
512 	netsec_write(priv, NETSEC_REG_NRM_TX_TXINT_TMR,  in netsec_et_set_coalesce()
514 	netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TXDONE);  in netsec_et_set_coalesce()
515 	netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TMREXP);  in netsec_et_set_coalesce()
522 	netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_PKTCNT,  in netsec_et_set_coalesce()
524 	netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_TMR,  in netsec_et_set_coalesce()
526 	netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_PKTCNT);  in netsec_et_set_coalesce()
527 	netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_TMREXP);  in netsec_et_set_coalesce()
805 		netsec_write(priv, NETSEC_REG_INTEN_SET,  in netsec_napi_poll()
912 	netsec_write(priv, NETSEC_REG_NRM_TX_PKTCNT, 1); /* submit another tx */  in netsec_netdev_start_xmit()
1017 		netsec_write(priv, reg, readl(ucode + i * 4));  in netsec_netdev_load_ucode_region()
1063 		netsec_write(priv, NETSEC_REG_DMA_HM_CTRL,  in netsec_reset_hardware()
1065 		netsec_write(priv, NETSEC_REG_DMA_MH_CTRL,  in netsec_reset_hardware()
1077 	netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RESET);  in netsec_reset_hardware()
1078 	netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RUN);  in netsec_reset_hardware()
1079 	netsec_write(priv, NETSEC_REG_COM_INIT, NETSEC_COM_INIT_REG_ALL);  in netsec_reset_hardware()
1085 	netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_UP,  in netsec_reset_hardware()
1087 	netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_LW,  in netsec_reset_hardware()
1090 	netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_UP,  in netsec_reset_hardware()
1092 	netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_LW,  in netsec_reset_hardware()
1096 	netsec_write(priv, NETSEC_REG_NRM_TX_CONFIG,  in netsec_reset_hardware()
1098 	netsec_write(priv, NETSEC_REG_NRM_RX_CONFIG,  in netsec_reset_hardware()
1112 	netsec_write(priv, NETSEC_REG_DMA_TMR_CTRL, priv->freq / 1000000 - 1);  in netsec_reset_hardware()
1113 	netsec_write(priv, NETSEC_REG_ADDR_DIS_CORE, 0);  in netsec_reset_hardware()
1123 	netsec_write(priv, NETSEC_REG_TOP_STATUS,  in netsec_reset_hardware()
1131 	netsec_write(priv, NETSEC_REG_DMA_MH_CTRL, MH_CTRL__MODE_TRANS);  in netsec_reset_hardware()
1132 	netsec_write(priv, NETSEC_REG_PKT_CTRL, value);  in netsec_reset_hardware()
1139 	netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, ~0);  in netsec_reset_hardware()
1142 	netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0);  in netsec_reset_hardware()
1172 	netsec_write(priv, MAC_REG_DESC_SOFT_RST, 1);  in netsec_start_gmac()
1176 	netsec_write(priv, MAC_REG_DESC_INIT, 1);  in netsec_start_gmac()
1203 	netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);  in netsec_start_gmac()
1204 	netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);  in netsec_start_gmac()
1226 	netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);  in netsec_stop_gmac()
1227 	netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);  in netsec_stop_gmac()
1253 		netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, val);  in netsec_irq_handler()
1257 		netsec_write(priv, NETSEC_REG_NRM_RX_STATUS, val);  in netsec_irq_handler()
1261 	netsec_write(priv, NETSEC_REG_INTEN_CLR, NETSEC_IRQ_RX | NETSEC_IRQ_TX);  in netsec_irq_handler()
1316 	netsec_write(priv, NETSEC_REG_INTEN_SET, NETSEC_IRQ_RX | NETSEC_IRQ_TX);  in netsec_netdev_open()
1338 	netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0);  in netsec_netdev_stop()
1726 	netsec_write(priv, NETSEC_REG_CLK_EN, 0);  in netsec_runtime_suspend()
1739 	netsec_write(priv, NETSEC_REG_CLK_EN, NETSEC_CLK_EN_REG_DOM_D |  in netsec_runtime_resume()